Features include 512Kbytes of Flash and up to 176Kbytes of SRAM with a maximum operating speed of 120MHz. Eight flexible communication units comprising USARTs, SPIs, and I2C-bus interfaces (TWIs), are some of the peripherals included. Three software-selectable, low-power modes are available on the G55G/G55J, sleep, wait, and backup.
Real-time event management permits peripherals to receive, react to, and send events in Active and Sleep modes without processor intervention. The flexible clock system provides the capability of having different clock frequencies for some peripherals, allowing for power consumption optimization.
Also without affecting the peripheral processing, the processor and bus clock frequency can be modified. Small package options of 49-pin WLCSP, 64-pin QFN, and 64-pin LQFP are combined with a rich and flexible peripheral set.
Features
- Core
- Arm Cortex-M4 with up to 16Kbytes SRAM on I/D bus providing 0 wait state execution at up to 120MHz
- Memory Protection Unit (MPU)
- DSP Instructions
- Floating Point Unit (FPU)
- Thumb®-2 instruction set
- Memory
- Up to 512Kbytes embedded Flash
- Up to 176Kbytes embedded SRAM
- 8Kbytes ROM with embedded boot loader, single-cycle access at full speed
- System
- Embedded voltage regulator for single-supply operation
- Power-on reset (POR) and Watchdog for safe operation
- Quartz or ceramic resonator oscillators: 3 to 20MHz with clock failure detection and 32.768kHz for RTT or system clock
- High-precision 8/16/24MHz factory-trimmed internal RC oscillator. In-application trimming access for frequency adjustment
- Slow clock internal RC oscillator as the permanent low-power mode device clock
- PLL range from 48MHz to 120MHz for device clock
- PLL range from 24MHz to 48MHz for a USB device and USB OHCI
- Up to 30 peripheral DMA (PDC) channels
- 256-bit General-Purpose Backup Registers (GPBR)
- 16 external interrupt lines
- Peripherals
- 8 flexible communication units supporting: USART, SPI, Two-wire Interface (TWI) featuring TWI masters and high-speed TWI slaves
- Crystal-less USB 2.0 Device and USB Host OHCI with On-chip Transceiver
- 2 Inter-IC Sound Controllers (I2S)
- 1 Pulse Density Modulation Interface (PDMIC) (supports up to two microphones)
- 2 three-channel 16-bit Timer/Counters (TC) with capture, waveform, compare, and PWM modes
- 1 48-bit Real-Time Timer (RTT) with 16-bit Prescaler and 32-bit counter
- 1 RTC with calendar and alarm features
- 1 32-bit Cyclic Redundancy Check Calculation Unit (CRCCU)
- I/O
- Up to 48 I/O lines with external interrupt capability (edge or level), debouncing, glitch filtering, and on-die series resistor termination.
- Individually programmable open-drain, pull-up, and pull-down resistor and synchronous output
- Two PIO Controllers provide control of up to 48 I/O lines
- Analog
- One 8-channel ADC, resolution up to 12 bits, sampling rate up to 500ksps
- Packages: 49-lead WLCSP, 64-lead LQFP, 64-lead QFN
- Operating Temperature Range: Industrial (-40°C to +85°C)