With 14 low-noise and configurable outputs, the HMC7043 clock buffers provide flexibility in interfacing the FPGA and ADC/DAC components in base transceiver station (BTS) systems. Each of the 14 channels features independent, flexible phase management. The RF SYNC feature deterministically synchronizes multiple HMC7043 clock buffers. This operation simplifies frame alignment between the components and ensures that all clock outputs start with the same edge. SPI-programmable power/performance adjustment ensures proper setup and holds times for the data converters.
The HMC7043 devices achieve <15fs rms jitter performance at 2457.6MHz to improve a high-speed data converter’s signal-to-noise ratio and dynamic range. The devices also have a very low noise floor of −155.2dBc/Hz at 983MHz to distribute frac-N LO signals with excellent spurious performance.