The single-ended reference input to the PLL operates up to 500MHz and features internal reference dividers and a multiplier for added flexibility. Additionally, the Phase Frequency Detector (PFD) comparison frequency can be up to 250MHz for integer mode and 160MHz for fraction-N mode.
The upconverter consists of an I/Q mixer that can operate in either I/Q mode with 500MHz of bandwidth or in IF (Intermediate Frequency) mode up to 3GHz of bandwidth, which allows various radio architectures and backward compatibility with legacy systems.
Immediately following the I/Q mixer are stages of gain and variable attenuation. The configuration can achieve a minimum 1dB compression point (P1dB) compression point of 19dBm, eliminating the need for external stages of gain.
A programmable 4-wire serial port interface (SPI) allows adjustment of the quadrature-phase for optimum sideband suppression. In addition, the SPI allows the nulling of LO feedthrough in IF mode. In I/Q mode, the LO feedthrough can be nulled by applying an external DC offset to the differential baseband I/Q inputs.
An IF automatic gain control (AGC) adjusts the IF variable gain amplifier (VGA) to compensate for input power variations. During normal operation, this AGC feature can be enabled or disabled via the SPI. When disabled during normal operation, the AGC feature only works on a test tone during power-down mode to track temperature variations.
The ADMV4530 Upconverter is available in a 40-terminal Land Grid Array (LGA) package and is RoHS compliant.