The first stage (PLL1) offers input reference conditioning by decreasing the jitter on a system clock. AD9528’s second stage PLL (PLL2) includes high-frequency clocks. These high-frequency clocks ensure low integrated jitter and low broadband noise from the clock output drivers. The external VCXO provides the low-noise reference required by PLL2 to have the restrictive phase noise and jitter requirements necessary for acceptable performance. AD9528’s on-chip VCO tunes from 3.45GHz to 4.025GHz. The integrated SYSREF generator outputs single shot, N-shot, or continuous signals synchronous to the PLL1 and PLL2 outputs to time-align multiple devices.
The AD9528 JESD204B Clock Generators generate two outputs (Output 1 and Output 2) with a maximum frequency of 1.25GHz, and 12 outputs up to 1GHz. Designers can configure each output to link directly from PLL1, PLL2, or the internal SYSREF generator. AD9528’s 14 output channels include a divider with coarse digital phase adjustment and an analog fine phase delay block. This allows complete flexibility in timing alignment across all 14 outputs.
Designers can use the AD9528 as a dual-input flexible buffer to distribute 14 device clock and/or SYSREF signals. At power-up, the AD9528 sends the VCXO signal directly to Output 12 and Output 13 to serve as the power-up ready clocks.