Analog Devices Inc. AD9177 16-bit DAC with Wideband Channelizers

Analog Devices Inc. AD9177 16-bit DAC with Wideband Channelizers provides flexible reconfigurable common platform design. The AD9177 is a highly integrated device with four 16-bit, 12 GSPS maximum sample-rate, and RF Digital-to-Analog Converter (DAC) cores supporting up to eight baseband channels. The device incorporates an 8-lane, 24.75Gbps JESD204C or 15.5Gbps JESD204B data receiver (JRx) port, an on-chip clock multiplier, and Digital Signal Processing (DSP) datapaths. These datapaths can be bypassed to allow a direct connection between the data receiver port and the DAC cores. The DSP datapaths are capable of processing complex signals for wide-band or multiband direct to RF applications, phase-array radar systems, and electronic warfare applications.

The AD9177 DAC can be operated without a data receiver port to generate multiple sine wave tones of varying frequencies in Direct Digital Synthesis (DDS) applications. Auxiliary features include low latency loopback mode, fast frequency hopping, power amplifier downstream protection circuitry, on-chip temperature monitoring unit, and flexible GPIO pins. Typical applications include wireless communications infrastructures, microwave point-to-point, E-band, 5G mm-wave, DOCSIS 3.1 and 4.0 CMTS, broadband communications systems, and phased-array radar and electronic warfare.

Features

Flexible and reconfigurable common platform design:
- 4 DAC cores connected to various DSP and bypass datapaths
- Supports single, dual, and quad-band
- Datapaths and DSP blocks are fully bypassable
- On-chip PLL with multichip synchronization
  - External RFCLK input option for off-chip PLL
DAC ac performance at 12 GSPS:
- 6.43mA to 37.75mA full-scale output current range
- -78.9dBc two-tone IMD3 (-7dBFS per tone)
- -155.1dBc/Hz NSD, single-tone at 3.7GHz
- -70dBc SFDR, single-tone at 3.7GHz
Versatile digital features:
- Selectable interpolation filters
- Configurable or bypassable DUCs
  - 8 fine complex DUCs and 4 coarse complex DUCs
  - 48-bit NCO per DUC
  - Option to bypass fine and coarse DUC
- Programmable delay per datapath
- Transmit DPD support
  - Fine DUC channel gain control and delay adjust

Maximum DAC sample rate up to 12 GSPS:
- Maximum data rate up to 12 GSPS using JESD204C
- Useable analog bandwidth to 8GHz
Auxiliary features:
- Direct digital synthesis and fast frequency hopping
- Low latency loopback mode (receive datapath NCO outputs can be routed to the transmit datapaths)
- Power amplifier downstream protection circuitry
- On-chip temperature monitoring unit
- Flexible GPIO pins
- TDD power savings option
SERDES JESD204B/JESD204C interface:
- 8-lane JESD204B/C receiver (JRx)
- JESD204B compliance with the maximum 15.5Gbps
- JESD204C compliance with the maximum 24.75Gbps
- Supports real or complex digital data (8-, 12-, 16-, or 24-bit)
15mm × 15mm, 324-ball BGA with 0.8mm pitch