Alliance Memory N25Q0x SPI NOR FLASH Memory Devices

Alliance Memory N25Q0x SPI NOR FLASH Memory Devices are high-performance multiple input/output serial Flash memories manufactured on 65nm NOR technology. These memory devices feature execute-in-place (XIP) functionality, a high-speed SPI-compatible bus interface, and advanced write protection mechanisms. The N25Q0x NOR FLASH memory devices can double or quadruple the transfer bandwidth for READ and PROGRAM operations. This is made possible by the innovative, high-performance, and dual and quad input/output instructions. These memory devices can be write-protected by software through volatile and nonvolatile protection features, depending on the application needs. The protection granularity is of 64KB (sector granularity) for volatile protections.

The N25Q0x SPI NOR FLASH memory devices have 64 One-Time Programmable (OTP) bytes that can be read and programmed with the READ OTP and PROGRAM OTP commands. These 64 bytes can also be permanently locked with a PROGRAM OTP command. These memory devices also have the ability to pause and resume PROGRAM and ERASE cycles by using dedicated PROGRAM/ERASE SUSPEND and RESUME instructions. The N25Q0x NOR FLASH memory devices can be operated with three different protocols including extended SPI, dual I/O SPI, and quad I/O SPI.

Features

SPI-compatible serial bus interface
108MHz (max) clock frequency
2.7V to 3.6V single supply voltage (N25Q032A)
1.7V to 2.0V single supply voltage (N25Q064A)
Dual/quad I/O instruction provides increased throughput up to 432MHz
Supported protocols:
- Extended SPI, dual I/O, and quad I/O
Execute-in-place (XIP) mode for all three protocols:
- Configurable via volatile or nonvolatile registers
- Enables memory to work in XIP mode directly after power-on
PROGRAM/ERASE SUSPEND operations
Continuous read of entire memory via a single command:
- Fast read
- Quad or dual output fast read
- Quad or dual I/O fast read
Flexible to fit application:
- Configurable number of dummy cycles
- Configurable output buffer
- RESET function available upon customer request (N25Q032A)
- Software reset (N25Q064A)

64-byte, user-lockable, one-time programmable (OTP) dedicated area
Erase capability:
- Subsector erase 4KB uniform granularity blocks
- Sector erase 64KB uniform granularity blocks
- Full-chip erase
Write protection:
- Software write protection applicable to every 64KB sector via volatile lock bit
- Hardware write protection: protected area size defined by four nonvolatile bits
- Additional smart protections, available upon request
Electronic signature:
- JEDEC-standard 2-byte signature
- Unique ID code (UID):
  - 17 read-only bytes, including:
    - Two additional extended device ID bytes to identify device factory options
    - Customized factory data (14 bytes)
Minimum 100,000 ERASE cycles per sector
More than 20 years data retention