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Accelerating RFSoC Solutions with Vitis Adam Taylor

(Source: Xilinx)

The Zynq® UltraScale+ RFSoC family of devices from Xilinx is a truly groundbreaking class of devices that fuse RF data converters with a high-performance processing system and programmable logic within a signal device. Notably, the RF data converter includes analog-to-digital converter (ADC) and digital-to-analog converter (DAC) and all the elements required to generate and process radio frequency signals. As such, the RF data converter provides digital up and down converters, mixers, and numerically controlled oscillators. The radio frequency system on chip (RFSoC) also has soft-decision, low-density parity-check forward-error correcting blocks that support the latest forward error correction (FEC) coding scheme to help maximize channel capacity.

This single silicon solution offers several advantages to the system developer, including a tightly integrated solution that significantly reduces the size and complexity of the circuit board and reduces overall power dissipation. The Zynq UltraScale+ RFSoC also provides the developer with a direct sampling solution. Direct sampling becomes enabled thanks to the ADC and DAC used within the RF data converter. These provide a high sampling frequency (10GSPS in Gen3 devices) and a wide analog input bandwidth (6GHz in Gen3 devices). Using a direct sampling approach removes the need for analog front ends, which provide up or down conversion. This offers significant system-level advantages as these analog front ends are not programmable or readily adaptable to support licensing or geographic restrictions, which often require the use of different frequency bands.

The Zynq UltraScale+ RFSoC also contains a 64-bit quad-core Arm® Cortex-A53 Application Processing Unit and a 32-bit dual-core Arm Cortex-R5 Real-time Processing Unit (Figure 1).

Figure 1: The Zynq UltraScale+ RFSoC Block Diagram outlines the solution structure. (Source Xilinx)

Real-time control and safety applications, along with high-performance applications, may be implemented within the Zynq UltraScale+ RFSoC processing system (PS). To support interfacing, the Zynq UltraScale+ RFSoC PS also provides support for multiple industry-standard interfaces, such as GigE, SATA, USB3, PCIe, CAN, I2C, SPI, and more. At the same time, the programmable logic, combined with the GTY Serializer/Deserializer (SERDES), provides the ability to support all Common Public Radio Interface (CPRI) line rates and up to 100GE.

Development of RFSoC solutions will strive to leverage the programmable logic in order to benefit from the throughput, determinism, and responsivity provided by its parallel structure. Of course, solutions implemented using a Zynq UltraScale+ RFSoC will be complex. Software-defined radios, RADAR, and test equipment are excellent examples. Developing and implementing these algorithms purely at the register-transfer level (RTL) can be very time consuming and impact the time to market.

One method that enables an optimal time to market while still allowing the developer to leverage the parallel nature of programmable logic is to use the Vitis unified software platform from Xilinx. Vitis enables users to accelerate algorithms from the processing system into the programmable logic. This acceleration is made possible thanks to high-level synthesis and OpenCL when working with Xilinx heterogeneous system-on-chip devices or acceleration cards.

Accelerating with Vitis and OpenCL

Vitis enables users to leverage the OpenCL framework to implement acceleration kernels within the programmable logic. These acceleration kernels have been defined using a higher-level language than a traditional RTL.

OpenCL is an industry-standard framework that supports parallel computing on heterogeneous systems. One of the core principles behind OpenCL is to enable cross-platform functionality without the need for code changes. This allows the same code to be portable across CPUs, GPUs, FPGAs, DSPs, etc., with the performance scaling depending upon the platform’s capabilities.

OpenCL uses a host and kernel model (Figure 2). Each system will have one host, which is typically x86-based, and several kernels that provide the acceleration and are usually GPU-, DSP-, or FPGA-based. To support the OpenCL flow, the host application is often developed in C/C++ and uses OpenCL APIs. These OpenCL APIs allow the host to manage the entire application lifecycle of loading, configuring, and executing kernels. While supporting cross-platform portability, the kernel is developed using the OpenCL C language, which is based upon C but has limitations to support cross-platform portability. 

This model allows the host program to be compiled using a standard compiler such as GCC or G++, while the kernel compiler is vendor-specific.  

Figure 2: The diagram shows how the Open CL structure enables a host program to use a standard compiler while the kernel uses a vendor-specific compiler. (Source: Xilinx)

When working with Xilinx heterogeneous system-on-chip devices, the Arm Application Processing Unit is the host, while the programmable logic instantiates kernels. Vitis provides the developer with everything required to generate, debug, and analyze both the host and kernel elements when targeting Xilinx heterogeneous SoC or acceleration cards.

Vitis Platform

To be able to leverage the Vitis OpenCL capabilities, a base platform is required. This base platform defines both hardware and software configuration of the underlying hardware. The hardware platform is created using the Vivado® Design Suite, makes available clocks, Advanced eXtensible Interface processing system/programmable logic (AXI PS/PL) interfaces, and interrupts the Vitis compiler. Using these interfaces, the Vitis compiler can connect the acceleration kernels into the processing system memory map. This allows for efficient data transfer using Direct Memory Access (DMA) and control of the kernels. The platform’s software element is provided by PetaLinux and provides an embedded Linux operating system that supports the Xilinx Run Time (XRT) (Figure 3).

Figure 3: The diagram illustrates the Vitis Platform Development Flow. (Source: Author)

Of course, the base platform developed in Vivado can also contain design elements and the hooks available to Vitis. In the case of the Zynq UltraScale+ RFSoC, the base design can include the necessary infrastructure to connect the RF Data Converters to external interfaces using the GTY transceivers or transferring data to and from the processor memory space.

Vitis Acceleration

Once the acceleration platform is available, developers can begin to develop their solution using Vitis. Using Vitis, they can implement control and configuration of the RF data converters and additional IP. The developers can then also implement the desired RF data-processing algorithm using C/C++ and OpenCL C to accelerate through bottlenecks and improve overall system performance.

To aid with the development of the algorithm, Vitis provides several open-source acceleration-ready libraries (Figure 4). These libraries include support for math, linear algebra, DSP, data compression, and, of course, AI.

Figure 4: The Vitis Development Environment provides open-source acceleration-ready libraries to aid in designing solutions. (Source: Author)

Once the software algorithms are implemented, the developer can use the software and hardware emulation flows provided by Vitis to optimize the algorithm for implementation in the programmable logic before generating the final boot image (Figure 5).

Figure 5: Vitis Application Development Flow optimizes the algorithm using SW and HW emulation in the programmable logic before creating the final boot image. (Source: Author)

To leverage the parallel nature of programmable logic, the developer might want to pipeline or unroll loops, organize memory, and AXI interfacing structures in the kernel. These optimizations are implemented using pragmas within the source code. Identifying the potential areas for optimizing the kernel code can be performed using the Vitis Analyzer and Vitis HLS analysis view (Figure 6).

Figure 6: Vitis Analyzer Platform View helps developers identify the potential areas for optimizing the kernel code. (Source: Author)

Once the optimization has been completed, the developer can build the final boot files and deploy the system for the next stage of testing and verification.

Wrap Up

The RFSoC, combined with Vitis’ OpenCL capabilities, provides the developer with a groundbreaking, tightly-coupled solution. This solution can provide the most responsive and deterministic solution by leveraging high-level languages, libraries, and frameworks. This development methodology enables a higher level, system-driven approach to solution implementation, which results in a reduced time to market.



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​Adam TaylorAdam Taylor is a professor of embedded systems, engineering leader, and world-recognized expert in FPGA/System on Chip and Electronic Design.


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