Spansion's S25 MirrorBit® Flash Non-Volatile Memory uses MirrorBit technology, which stores two data bits in each memory array transistor; Eclipse architecture, which dramatically improves program and erase performance; and 65 nm process lithography. This family of devices connect to a host system via a Serial Peripheral Interface (SPI). Traditional SPI single bit serial input and output (SIngle I/O or SIO) is supported as well as optional two bit (Dual I/O or DIO) and four bit (Quad I/O or QIO) serial commands. In addition, the FL-S family adds support for Double Data Rate (DDR) read commands for SIO, DIO, and QIO that transfer address and read data on both edges of the clock. The Eclipse architecture features a Page Programming Buffer that allows up to 128 words (256 bytes) or 256 words (512 bytes) to be programmed in one operation, resulting in faster effective programming and erase than prior generation SPI program or erase algorithms. S25 MirrorBit® Flash Non-Volatile Memory is ideal for code shadowing, XIP, and data storage.