Integrated Device Technology 85102 / 85104 / 85108 HCSL Buffers are low skew, high performance members of the HiPerClockS™ family of high-performance clock solutions. IDT 85102 is a 1-to-2 Differential-to-HCSL fanout buffer with a differential clock input. The CLK0, nCLK0 input pair can accept most standard differential input levels. The clock enable is internally synchronized to eliminate runt clock pulses on the output during asynchronous assertion/deassertion of the clock enable pin. IDT 85104 is a 1-to-4 Differential/LVCMOS-to-0.7V HCSL fanout buffer with two selectable clock inputs. The CLK0, nCLK0 pair can accept most standard differential input levels. The single-ended CLK1 can accept LVCMOS or LVTTL input levels. IDT 85108 is a 1-to-8 Differential-to-0.7V HCSL clock distribution chip that can accept most differential input levels and translates them to 3.3V HCSL output levels. 85108 provides a low power, low noise, low skew, point-to-point solution for distributing HCSL clock signals. Guaranteed output and part-to-part skew characteristics make IDT 85102 / 85014 / 85108 devices ideal for applications demanding well-defined performance and repeatability.