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These devices include the highest PCIe switch lane counts in the industry, at 96 and 80 lanes. These switches are PCI-SIG® PCIe 2.0 (Gen 2) specification-compliant with unique PLX-only features, including support for x16 port configurations, integrated non-transparency (NT) ports and a suite of performance-enhancing and system de-bug tools that empower system architects.

The PLX ExpressLane™ PEX 8696 (96 lanes, 24 ports), PEX 8680 (80 lanes, 20 ports), PEX 8664 (64 lanes, 16 ports) and PEX 8649 (48 lanes, 12 ports) allow designers to build switch fabrics, redundant backplanes and complex storage applications without having to deal with high latency, high power consumption and bandwidth limitations associated with using multiple smaller switch chips.

• 48-lane, 12-port PCIe Gen2 switch
• Integrated 5.0 GT/s SerDes
• 27 x 27mm2, 676-ball FCBGA package
• Typical Power: 6.7 Watts

• 64-lane, 16-port PCIe Gen2 switch
• Integrated 5.0 GT/s SerDes
• 35 x 35mm2, 1156-ball FCBGA package
• Typical Power: 7.9 Watts
  

• 80-lane, 20-port PCIe Gen2 switch
• Integrated 5.0 GT/s SerDes
• 35 x 35mm2, 1156-ball FCBGA package
• Typical Power: 9.0 Watts

• 96-lane, 24-port PCIe Gen2 switch
• Integrated 5.0 GT/s SerDes
• 35 x 35mm2, 1156-ball FCBGA package
• Typical Power: 10.2 Watts

The PEX 86xx employs an enhanced version of PLX’s field tested PEX 8648 PCIe switch architecture, which allows users to configure the device in legacy single-host mode or multi-host mode with up to six host ports capable of 1+1 (one active & one backup) or N+1 (N active & one backup) host failover. This powerful architectural enhancement enables users to build PCIe based systems to support high-availability, failover, redundant and clustered systems.

The PEX 86xx architecture supports packet cut-thru with a maximum latency of 176ns (x16 to x16). This, combined with large packet memory, flexible common buffer/FC credit pool and non-blocking internal switch architecture, provides full line rate on all ports for performance-hungry applications such as servers and switch fabrics. The low latency enables applications to achieve high throughput and performance. In addition to low latency, the device supports a packet payload size of up to 2048 bytes, enabling the user to achieve even higher throughput.

In Multi-Host mode, PEX 86xx can be configured with up to four upstream host ports, each with its own dedicated downstream ports. The device can be configured for 1+1 redundancy or N+1 redundancy. The PEX 86xx allows the hosts to communicate their status to each other via special door-bell registers. In failover mode, if a host fails, the host designated for failover will disable the upstream port attached to the failing host and program the downstream ports of that host to its own domain. The Figure below shows a two host system in Multi-Host mode with two virtual switches inside the device and shows Host 1 disabled after failure and Host 2 having taken over all of Host 1’s end-points.

In Single-Host mode, the PEX 86xx supports a Non-Transparent (NT) Port, which enables the implementation of dual-host systems for redundancy and host failover capability. The NT port allows systems to isolate host memory domains by presenting the processor subsystem as an endpoint rather than another memory system. Base address registers are used to translate addresses; doorbell registers are used to send interrupts between the address domains; and scratchpad registers (accessible by both CPUs) allow inter-processor communication.