Analog Devices AD9691 14-bit dual analog-to-digital converter (ADC) is a 1.25GSPS JESD204B ADC designed for sampling wide bandwidth analog signals up to 1.5GHz. The device includes an on-chip buffer and sample-and-hold circuit for low power, small size, and ease-of-use. The dual, low power consumption ADC cores have a multistage, differential pipelined architecture with integrated output error correction logic. Each device includes wide bandwidth inputs to support a variety of user-selectable input ranges. The ADC data outputs are internally connected to two digital downconverters (DDCs). The DDC consists of four cascaded signal processing stages: a 12-bit frequency translator (NCO) and four half-band decimation filters. In addition to the DDC blocks, the AD9691 offers several functions that simplify the automatic gain control (AGC) function in the communications receiver. The programmable threshold detector enables monitoring of the incoming signal power using the fast detect output bits of the ADC. Because the threshold indicator has low latency, the designer can quickly turn down the system gain to avoid an overrange condition at the ADC input. Designers can configure the Subclass 1 JESD204B-based high speed serialized output in a variety of one-, two-, four- or eight-lane configurations, depending on the DDC configuration and the acceptable lane rate of the receiving logic device. The SYSREF± input pins support multiple device synchronization. Rated at 1.9W per channel, the AD9691 ADC is well-suited for communications, spectrum analyzers, network analyzers, integrated RF test solutions, DOCSIS 3.x CMTS upstream receive paths, and high speed data acquisition systems.