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Home » NEWEST Products » New by Category » Semiconductors » Chipsets » Chipset Memory Controller Hub (MCH) - Intel
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Intel Chipset Memory Controller Hubs (MCH)

Intel's Chipset Memory Controller Hubs (MCH) are designed for use with Intel processors that enables the use of a Memory Controller Hub (MCH) and I/O Controller to reduced power consumption and improve reliability. The 3010/5000P MCH each contains a Memory Controller Hub (MCH) for the host bridge and the I/O controller hub for the I/O subsystem. The 945G Express Chipsets deliver innovative features for interactive clients and many other embedded computing solutions requiring enhanced graphics capabilities. The E7320/E7520 Memory Controller Hub (MCH) are the next generation Intel dual-processor chipset technology that enables reduced power consumption, improved platform reliability and system manageability compared to previous generation server platforms.

3010 Chipset Memory Controller Hub (MCH)

Intel's 3010 Chipset Memory Controller Hub (MCH) is designed for use with Intel Pentium 4 processor 600 Sequence, Intel Pentium D processor 800 Sequence and 900  Sequence, Intel Celeron D, and Dual-Core Intel Xeon Processor 3000 Series in the LGA775 package in entry-level UP server platforms. The chipset contains two components: Memory Controller Hub (MCH) and Intel I/O Controller Hub 7 (ICH7). The MCH provides the interface to the processor, main memory, PCI Express, and the ICH7. The ICH7 is the seventh generation I/O Controller Hub and provides a multitude of I/O related functions.

Additional Resources

Datasheet Datasheet
Datasheet Product Brief
Datasheet Specification Update
Datasheet Thermal & Mechanical Guidelines



Learn More
Learn More About Intel Desktop Express Chipsets Intel Desktop Chipsets

Features
  • Supports a single Intel Pentium 4, Intel Pentium D, Intel Celeron D, and Dual-Core Intel® Xeon® Processor
  • Supports Pentium 4 processor FSB interrupt delivery
  • 533/800/1066 MT/s (133/200/266 MHz core) FSB
  • Supports Hyper-Threading Technology (HT Technology)
  • FSB Dynamic Bus Inversion (DBI)
  • 36-bit host addressing for access to 8 GB of memory space
  • 12-deep In-Order Queue
  • 1-deep Defer Queue>
  • GTL+ bus driver with integrated GTL termination resistors
  • Supports a Cache Line Size of 64 bytes
  • A chip-to-chip connection interface to Intel ICH7
  • 2 GB/s point-to-point DMI to ICH7 (1 GB/s each direction)
  • 100 MHz reference clock (shared with PCI Express Interface)
  • 32-bit downstream addressing
  • Messages and Error Handling
  • PCI Express Interface Support: two PCI Express ports (two x8/x4/x1, or one x16)
  • Peer-to-peer Writes
  • Compatible with the PCI Express Base
  • Raw bit rate on data pins of 2.5 Gb/s resulting in a real bandwidth per pair of 250 MB/s
  • Maximum theoretical aggregate bandwidth of 8 GB/s when x16
  • 8 GB maximum memory
  • Up to two 64-bit wide DDR2 SDRAM channels

  • DDR2 memory DIMM frequencies of 533 MHz and 667 MHz
  • Asymmetric or Interleaved modes
  • Bandwidth up to 10.7 GB/s (DDR2 667) in dual- channel Interleaved mode
  • ECC (Error Correcting Code) memory
  • 256 Mb, 512 Mb and 1 Gb DDR2 technologies
  • Four banks for DDR2 devices up to 512 Mb density; eight banks for 1 Gb DDR2 devices
  • Unbuffered DIMMs only
  • Page sizes of 4 KB, 8 KB, and 16 KB
  • Opportunistic refresh
  • Up to 64 simultaneously open pages
  • SPD (Serial Presence Detect) scheme for DIMM detection support
  • Supports configurations defined in the JEDEC DDR2 DIMM specification only
Memory Specifications
  • 8GB Max Memory Size (dependent on memory type)
  • DDR2-533/DDR2-667 Memory Types
  • 2 Memory Channels
  • 10.7 GB/s Max Memory Bandwidth
  • 36-bit Physical Address Extensions
  • ECC Memory Supported
Expansion Options
  • PCI Express Revision 1.1
  • 2x8/x4/x1 or 1x16 PCI Express Configurations
Package Specifications
  • 1 Max CPU Configuration
  • 105ºC TCASE
  • 34.0mm x 34.0mm package size
  • Low Halogen Options Available: See MDDS
Block Diagram
Block Diagram 
 

5000P Chipset Memory Controller Hub (MCH)

Intel's 5000P Chipset Memory Controller Hub (MCH) is designed for systems based on the Dual-Core Intel Xeon 5000 sequence and supports a FSB frequency up to 1333 MTS. The Intel 5000P chipset contains two main components: Memory Controller Hub (MCH) for the host bridge and the I/O controller hub for the I/O subsystem. The Intel 5000P chipset uses the Intel 631xESB/632xESB I/O Controller Hub.

Additional Resources

Datasheet Datasheet
Datasheet Product Brief
Datasheet Specification Update
Datasheet Thermal & Mechanical Guidelines



Learn More
Learn More About Intel Desktop Express Chipsets Intel Desktop Chipsets

Features
  • Supports two Dual-Core Intel Xeon processor 5000 series
  • 1066 and 1333 MHz dual independent buses - increaed platform system bus bandwidth delivers outstanding performance
  • PCI Express (PCIe) - provides a direct connection between the MCH and PCI Express compoents/adapters with bandwidth up to 4GB/second on each PCI Express x8 interface
  • FBDIMM 53.3 MHz and 667 MHz memory interface
  • Intel 6700PXH 64-bit PCI Hub
  • Advanced Platform RAS with features such as memory ECC, Intel x4 and x8 Single Device Data Correction (SDDC), DIMM sparing, and memory mirroring for improved system reliability
Expansion Options
  • PCI Express Revision 1.1
  • 4x4 PCI Express Configurations
Memory Specifications
  • 64GB Max Memory Size (dependent on memory type)
  • DDR2-533-FBDIMM/DDR2-667-FBDIMM Memory Types
  • 4 Memory Channels
  • 21GB/s Max Memory Bandwidth
  • 36-bit Physical Address Extensions
  • ECC Memory Supported
Package Specifications
  • 2 Max CPU Configuration
  • 105ºC TCASE
  • 42.5mm x 42.5mm package size
  • Low Halogen Options Available: See MDDS
Block Diagram
Block Diagram 
 

E7320 Memory Controller Hub (MCH)

Intel's E7320 Memory Controller Hub (MCH) are the next generation Intel dual-processor chipset technology that enables reduced power consumption, improved platform reliability and system manageability compared to previous generation server platforms. This chipset enable new dual-processor servers to deliver outstanding performance, dependability and value to enterprise front-end, small-medium business (SMB) and high performance computing (HPC) applications.



The Intel E7320 chipsets include revolutionary PCI Express serial I/O technology and DDR2, the next generation memory technology to help increase I/O bandwidth and reduce system latency for data-intensive applications. The Intel Xeon Processor with 800MHz system bus allows these chipsets to support the Intel Xeon processor with Intel Extended Memory 64 Technology (Intel EM64T), Hyper-Treading technology, Enhanced Intel SpeedStep Technology and Streaming SIMD Extensions 3 (SSE3) Instructions.

Additional Resources

Datasheet Datasheet
Datasheet Product Brief
Datasheet Specification Update
Datasheet Thermal & Mechanical Guideline


Learn More
Learn More About Intel Desktop Express Chipsets Intel Desktop Chipsets

Features
  • Supports Intel Xeon Processors with 800 MHz system bus (2X address, 4X data)
  • Symmetric Multiprocessing Protocol (SMP) for up to two processors at 800 MHz
  • Parity protection on address, data, request, and response signals
  • Supports Hyper-Threading Technology
  • Dynamic Bus Inversion (DBI)
  • 36-bit host interface addressing support
  • 12-deep in-order queue
  • AGTL+ technology with on-die termination
  • Support for 128Mb (DDR266 and DDR333 only), 256Mb, 512Mb, and 1Gb DRAM densities
  • Up to two registered memory DDR channels operating in lock-step at DDR266, DDR333 or DDR2-400
  • Data bandwidth per channel of 2.13GB/s (DDR266), 2.67GB/s (DDR333) or 3.2GB/s (DDR2-400)
  • Maximum memory size 32GB (DDR266) or 16GB (DDR333 and DDR2-400)
  • Hardware memory initialization
  • Integrated four-channel DMA engine with IOxAPIC functionality
  • Three x8 PCI Express interfaces (each of these interfaces can be configured as two independent x4 interfaces)
  • 32-bit CRC and hardware link-level retry
  • Compatible with PCI Express Interface
  • High bandwidth connection of 4GB/s per x8 port to I/O processor, PCI-X, Ethernet, or Infiniband Technology bridge devices
  • Supports 36-bit addressing using 64-bit semantics
  • Support for peer segment destination write traffic between PCI Express ports
  • Support for non-snooped traffic to memory
  • Support for remote boot
  • Support for link active-state and ACPI power management
  • 266MB/s interface to Intel 82801ER ICH5R or 6300ESB ICH via HI 1.5
  • Parity protected
  • Support for differentiated, high priority requests
  • 32-bit downstream addressing
  • 64-bit upstream addressing (full DAC support) truncated to 36 bits internally
  • Power management messaging
  • Support for automatic read retry on uncorrectable errors
  • Support for RAS fail-over to an on-line spare DIMM
  • Support for memory mirroring
  • Hardware periodic memory scrubbing, including demand scrub support
  • Full access to configuration registers via SMBus and IEEE 1149.1 JTAG ports
  • Support for Intel x4 Single Device Data Correction (x4 SDDC)
  • Support for standard SEC-DED (72, 64) ECC on each channel when x4 SDDC technology is disabled
Memory Specifications
  • 32GB Max Memory Size (dependent on memory type)
  • DDR-266 (32GB)/DDR-333 (16GB)/DDR2-400 (16GB) Memory Types
  • 2 Memory Channels
  • 6.4GB/s Max Memory Bandwidth
  • 36-bit Physical Address Extensions
  • ECC Memory Supported
Expansion Options
  • PCI Express Revision 1.1
  • 1x8 PCI Express Configurations
Package Specifications
  • 2 Max CPU Configuration
  • 42.5mm x 42.5mm package size
  • Low Halogen Options Available: See MDDS
Block Diagram
Block Diagram 
 

E7520 Memory Controller Hub (MCH)

Intel's E7520 Memory Controller Hub (MCH) are the next generation Intel dual-processor chipset technology that enables reduced power consumption, improved platform reliability and system manageability compared to previous generation server platforms. This chipset enable new dual-processor servers to deliver outstanding performance, dependability and value to enterprise front-end, small-medium business (SMB) and high performance computing (HPC) applications.



The Intel E7520 chipsets include revolutionary PCI Express serial I/O technology and DDR2, the next generation memory technology to help increase I/O bandwidth and reduce system latency for data-intensive applications. The Intel Xeon Processor with 800MHz system bus allows these chipsets to support the Intel Xeon processor with Intel Extended Memory 64 Technology (Intel EM64T), Hyper-Treading technology, Enhanced Intel SpeedStep Technology and Streaming SIMD Extensions 3 (SSE3) Instructions.

Additional Resources

Datasheet Datasheet
Datasheet Product Brief
Datasheet Specification Update
Datasheet Thermal & Mechanical Guidelines



Learn More
Learn More About Intel Desktop Express Chipsets Intel Desktop Chipsets

Features
  • Supports Intel Xeon Processors with 800 MHz system bus (2X address, 4X data)
  • Symmetric Multiprocessing Protocol (SMP) for up to two processors at 800 MHz
  • Parity protection on address, data, request, and response signals
  • Supports Hyper-Threading Technology
  • Dynamic Bus Inversion (DBI)
  • 36-bit host interface addressing support
  • 12-deep in-order queue
  • AGTL+ technology with on-die termination
  • Support for 128Mb (DDR266 and DDR333 only), 256Mb, 512Mb, and 1Gb DRAM densities
  • Up to two registered memory DDR channels operating in lock-step at DDR266, DDR333 or DDR2-400
  • Data bandwidth per channel of 2.13GB/s (DDR266), 2.67GB/s (DDR333) or 3.2GB/s (DDR2-400)
  • Maximum memory size 32GB (DDR266) or 16GB (DDR333 and DDR2-400)
  • Hardware memory initialization
  • Integrated four-channel DMA engine with IOxAPIC functionality
  • Three x8 PCI Express interfaces (each of these interfaces can be configured as two independent x4 interfaces)
  • 32-bit CRC and hardware link-level retry
  • Compatible with PCI Express Interface
  • High bandwidth connection of 4GB/s per x8 port to I/O processor, PCI-X, Ethernet, or Infiniband Technology bridge devices
  • Supports 36-bit addressing using 64-bit semantics
  • Support for peer segment destination write traffic between PCI Express ports
  • Support for non-snooped traffic to memory
  • Support for remote boot
  • Support for link active-state and ACPI power management
  • 266MB/s interface to Intel 82801ER ICH5R or 6300ESB ICH via HI 1.5
  • Parity protected
  • Support for differentiated, high priority requests
  • 32-bit downstream addressing
  • 64-bit upstream addressing (full DAC support) truncated to 36 bits internally
  • Power management messaging
  • Support for automatic read retry on uncorrectable errors
  • Support for RAS fail-over to an on-line spare DIMM
  • Support for memory mirroring
  • Hardware periodic memory scrubbing, including demand scrub support
  • Full access to configuration registers via SMBus and IEEE 1149.1 JTAG ports
  • Support for Intel x4 Single Device Data Correction (x4 SDDC)
  • Support for standard SEC-DED (72, 64) ECC on each channel when x4 SDDC technology is disabled
Memory Specifications
  • 32GB Max Memory Size (dependent on memory type)
  • DDR-266 (32GB)/DDR-333 (16GB)/DDR2-400 (16GB) Memory Types
  • 2 Memory Channels
  • 6.4GB/s Max Memory Bandwidth
  • 36-bit Physical Address Extensions
  • ECC Memory Supported
Expansion Options
  • PCI Express Revision 1.1
  • 3x8 PCI Express Configurations
Package Specifications
  • 2 Max CPU Configuration
  • 42.5mm x 42.5mm package size
  • Low Halogen Options Available: See MDDS
Block Diagram
Block Diagram 
 
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