• Order Now
• View Product List
• More About PLX Technology

View Product List

PLX Technology ExpressLane PEX 86xx PCIe Switches

PLX Technology ExpressLane™ PEX 86xx is the industry's largest PCI Express Gen 2 Switch. The PLX Technology PEX 86xx offers Multi-Host PCI Express switching capability enabling users to connect multiple hosts to their respective endpoints via scalable, high bandwidth, non-blocking interconnection to a wide variety of applications, including servers, storage systems, and communications platforms. The PEX 86xx uses an enhanced version of the field tested PLX Technology PEX 8648 PCIe switch architecture, which allows users to configure the device in legacy single-host mode or multi-host mode with up to eight host ports capable of 1+1 (one active and one backup) or N+1 (N active and one backup) host failover. This PCI Express Gen 2 Switch supports packet cut-thru with a maximum latency of 176ns (x16 to x16).

• 6-lane, 6-port, PCIe Gen2 switch
• Integrated 5.0 GT/s SerDes
• 15x15mm 196-ball PBGA Package

• 16-lane, 4-port, PCIe Gen2 switch
• Integrated 5.0 GT/s SerDes
• 19x19mm 324-ball FCBGA Package

• 24-lane, 6-port, PCIe Gen2 switch
• Integrated 5.0 GT/s SerDes
• 19x19mm 324-ball FCBGA Package

• 32-lane, 12-port, PCIe Gen2 switch
• Integrated 5.0 GT/s SerDes
• 27x27mm 676-ball FCBGA Package

• 48-lane, 12-port PCIe Gen2 switch
• Integrated 5.0 GT/s SerDes
• 27x27 676-ball FCBGA Package

• 48-lane, 12-port PCIe Gen2 switch
• Integrated 5.0 GT/s SerDes
• 27 x 27mm2, 676-ball FCBGA package
• Typical Power: 6.7 Watts

• 64-lane, 16-port, PCIe Gen2 switch
• Integrated 5.0 GT/s SerDes
• 35x35mm 1156-ball FCBGA Package
• Typical Power: 7.9 Watts

• 96-lane, 24-port PCIe Gen2 switch
• Integrated 5.0 GT/s SerDes
• 35 x 35mm2, 1156-ball FCBGA package
• Typical Power: 10.2 Watts

The PEX 86xx employs an enhanced version of PLX’s field tested PEX 8648 PCIe switch architecture, which allows users to configure the device in legacy single-host mode or multi-host mode with up to six host ports capable of 1+1 (one active & one backup) or N+1 (N active & one backup) host failover. This powerful architectural enhancement enables users to build PCIe based systems to support high-availability, failover, redundant and clustered systems.

The PEX 86xx architecture supports packet cut-thru with a maximum latency of 176ns (x16 to x16). This, combined with large packet memory, flexible common buffer/FC credit pool and non-blocking internal switch architecture, provides full line rate on all ports for performance-hungry applications such as servers and switch fabrics. The low latency enables applications to achieve high throughput and performance. In addition to low latency, the device supports a packet payload size of up to 2048 bytes, enabling the user to achieve even higher throughput.

In Multi-Host mode, PEX 86xx can be configured with up to four upstream host ports, each with its own dedicated downstream ports. The device can be configured for 1+1 redundancy or N+1 redundancy. The PEX 86xx allows the hosts to communicate their status to each other via special door-bell registers. In failover mode, if a host fails, the host designated for failover will disable the upstream port attached to the failing host and program the downstream ports of that host to its own domain. The Figure below shows a two host system in Multi-Host mode with two virtual switches inside the device and shows Host 1 disabled after failure and Host 2 having taken over all of Host 1’s end-points.

In Single-Host mode, the PEX 86xx supports a Non-Transparent (NT) Port, which enables the implementation of dual-host systems for redundancy and host failover capability. The NT port allows systems to isolate host memory domains by presenting the processor subsystem as an endpoint rather than another memory system. Base address registers are used to translate addresses; doorbell registers are used to send interrupts between the address domains; and scratchpad registers (accessible by both CPUs) allow inter-processor communication.