Maxim MAXREFDES34 Alcatraz Reference Design
Maxim's MAXREFDES34 Alcatraz Reference Design is a subsystem that provides a reference design for securing Xilinx FPGAs to protect IP and prevent attached peripheral counterfeiting. The system implements a SHA-256 challenge-response between the FPGA and a DS28E15 secure authenticator. The DS28E15 communicates over the single-contact 1-Wire® bus, reducing the number of pins necessary to carry out the solution. The reference code defines a combined SHA-256 processor and 1-Wire Master of the host FPGA.