Contact Mouser (USA)  (800) 346-6873     |     Feedback        
View Cart     |     Change Location  USD
United States United States

Please confirm your currency selection:

US Dollars
Home » NEWEST Products » New by Manufacturer » Integrated Device Technology (IDT) » IDT 85102 / 85104 / 85108 HCSL Buffers
NEWEST Products
IDT 85102 / 85104 / 85108 HCSL Buffers
IDT 85102 / 85104 / 85108 HCSL Buffers

View Product List

Additional Resources

IDT 85102 / 85104 / 85108 HCSL Buffers

Integrated Device Technology 85102 / 85104 / 85108 HCSL Buffers are low skew, high performance members of the HiPerClockS™ family of high-performance clock solutions. IDT 85102 is a 1-to-2 Differential-to-HCSL fanout buffer with a differential clock input. The CLK0, nCLK0 input pair can accept most standard differential input levels. The clock enable is internally synchronized to eliminate runt clock pulses on the output during asynchronous assertion/deassertion of the clock enable pin.  IDT 85104 is a 1-to-4 Differential/LVCMOS-to-0.7V HCSL fanout buffer with two selectable clock inputs. The CLK0, nCLK0 pair can accept most standard differential input levels. The single-ended CLK1 can accept LVCMOS or LVTTL input levels. IDT 85108 is a 1-to-8 Differential-to-0.7V HCSL clock distribution chip that can accept most differential input levels and translates them to 3.3V HCSL output levels. 85108 provides a low power, low noise, low skew, point-to-point solution for distributing HCSL clock signals. Guaranteed output and part-to-part skew characteristics make IDT 85102 / 85014 / 85108 devices ideal for applications demanding well-defined performance and repeatability.


85102 Features
  • Two 0.7V differential HCSL outputs
  • Selectable differential CLK0, nCLK0 or LVCMOS inputs
  • CLK0, nCLK0 pair can accept the following differential input levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL
  • CLK1 can accept the following input levels: LVCMOS or LVTTL
  • Maximum output frequency: 500MHz
  • Translates any single-ended input signal to 3.3V
  • HCSL levels with resistor bias on nCLK input
  • Output skew: 65ps (max)
  • Part-to-part skew: 600ps (max)
  • Propagation delay: 3.2ns (max)
  • Additive phase jitter, RMS: 0.14ps typical @ 250MHz
  • 3.3V operating supply
  • -40°C to 85°C ambient operating temperature

Block Diagram
85102 Block Diagram
85104 Features
  • Four 0.7V differential HCSL outputs
  • Selectable differential CLK0, nCLK0 or LVCMOS inputs
  • CLK0, nCLK0 pair can accept the following differential input levels: LVPECL, LVDS, LVHSTL, HCSL
  • CLK1 can accept the following input levels: LVCMOS or LVTTL
  • Maximum output frequency: 500MHz
  • Translates any single-ended input signal to 3.3V
  • HCSL levels with resistor bias on nCLK input
  • Output skew: 100ps (max)
  • Part-to-part skew: 600ps (max)
  • Propagation delay: 3.2ns (max)
  • Additive phase jitter, RMS: 0.22ps (typical)
  • 3.3V operating supply
  • -40°C to 85°C ambient operating temperature

Block Diagram
85104 Block Diagram
85108 Features
  • Eight 0.7V differential HCSL clock output pairs
  • CLK/nCLK input pair can accept the following differential input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL
  • Maximum output frequency: 500MHz
  • Additive phase jitter, RMS: 0.09ps (typical)
  • Output skew: 80ps (max)
  • Part-to-part skew: 400ps (max)
  • Propagation delay: 3ns (max)
  • Full 3.3V operating supply
  • -40°C to 85°C ambient operating temperature

Block Diagram
85108 Block Diagram
  • Integrated Device Technology (IDT)
  • Semiconductors|Integrated Circuits|IC-Clock & Timer