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Home » NEWEST Products » New by Manufacturer » Altera Corporation » Altera Stratix® V High Bandwidth FPGAs
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Altera Stratix IV High Density High-Performance FPGAs

Altera Stratix® V High Bandwidth FPGAs

Altera's Stratix® V High Bandwidth FPGAs deliver the industry's highest bandwidth, highest level of system integration, and ultimate flexibility with reduced cost and the lowest total power for high-end applications. Advantages of the Stratix® V include the ability to attain breakthrough bandwidth with power-efficient transceivers, achieve higher integration on a single chip and reduce costs, get ultimate flexibility in your designs and lower your system power. The Stratix® V is offered in four different variants.

Altera Stratix® V E (Enhanced) High Bandwidth FPGAs

Altera's Stratix® V High Bandwidth FPGAs deliver the industry's highest bandwidth, highest level of system integration, and ultimate flexibility with reduced cost and the lowest total power for high-end applications. Advantages of the Stratix® V include the ability to attain breakthrough bandwidth with power-efficient transceivers, achieve higher integration on a single chip and reduce costs, get ultimate flexibility in your designs and lower your system power. Stratix® V E FPGAs offers up to 950K logic elements (LEs), 52-megabit (Mb) RAM, 704 18x18 high-performance, variable-precision multipliers, and 840 I/Os. The E variant is optimized for ASIC prototyping with 952K logic elements on the highest performance logic fabric.

Features
  • 28-nm TSMC process technology
  • Low-power serial transceivers
  • General-purpose I/Os (GPIOs)
  • Embedded HardCopy® Block
  • Embedded transceiver hard IP
  • Power Management
    • Programmable Power Technology
    • Quartus II integrated PowerPlay Power Analysis
  • High-performance core fabric
  • Enhanced ALM with four registers
  • Embedded memory blocks
    • M20K: 20-Kbit with hard error correction code (ECC)
    • MLAB: 640-bit
  • Variable precision DSP blocks

  • Fractional PLLs
  • Clock networks
    • 717-MHz fabric clocking
    • Global, quadrant, and peripheral clock networks
  • Device Configuration
    • Serial and parallel flash interface
    • Enhanced advanced encryption standard (AES) design
      security features
    • Tamper protection
    • Partial and dynamic reconfiguration
    • Configuration via Protocol (CvP)
  • High-performance packaging
  • HardCopy® V migration
Stratix® V  E Family Features
Feature 5SEE9 5SEEB
Logic Elements (K) 840 952
Registers (K) 1,268 1,437
Fractional PLLs 28 28
M20K Memory Blocks 2,640 2,640
M20K Memory (Mbits) 52 52
Variable Precision Multipliers (18x18) 704 704
Variable Precision Multipliers (27x27) 352 352
DDR3 SDRAM x72 DIMM Interfaces 6 6

Altera Stratix® V GX High Bandwidth FPGAs

Altera's Stratix® V High Bandwidth FPGAs deliver the industry's highest bandwidth, highest level of system integration, and ultimate flexibility with reduced cost and the lowest total power for high-end applications. Advantages of the Stratix® V include the ability to attain breakthrough bandwidth with power-efficient transceivers, achieve higher integration on a single chip and reduce costs, get ultimate flexibility in your designs and lower your system power. Stratix® V GX FPGAs with transceivers offer to integrate up to 66 full-duplex, 14.1-Gbps transceivers and up to 6 x72-bit DIMM DDR3 memory interfaces supporting 1,066 MHz. The GX variant is optimized for high-performance, high-bandwidth applications with integrated transceivers supporting backplane, chip-to-chip, and chip-to-module operation at up to 14.1 Gbps

Features
  • 28-nm TSMC process technology
  • Low-power serial transceivers
  • General-purpose I/Os (GPIOs)
  • Embedded HardCopy® Block
  • Embedded transceiver hard IP
  • Power Management
    • Programmable Power Technology
    • Quartus® II integrated PowerPlay Power Analysis
  • High-performance core fabric
  • Enhanced ALM with four registers
  • Embedded memory blocks
    • M20K: 20-Kbit with hard error correction code (ECC)
    • MLAB: 640-bit
  • Variable precision DSP blocks

  • Fractional PLLs
  • Clock networks
    • 717-MHz fabric clocking
    • Global, quadrant, and peripheral clock networks
  • Device Configuration
    • Serial and parallel flash interface
    • Enhanced advanced encryption standard (AES) design
      security features
    • Tamper protection
    • Partial and dynamic reconfiguration
    • Configuration via Protocol (CvP)
  • High-performance packaging
  • HardCopy® V migration
Stratix® V  GX Family Features 
Feature 5SGXA3 5SGXA4 5SGXA5 5SGXA7 5SGXA9 5SGXAB 5SGXB5 5SGXB6 5SGXB9 5SGXBB
Logic Elements (K) 340 420 490 622 840 952 490 597 840 952
Registers (K) 513 634 740 939 1,268 1,437 740 902 1,268 1,437
14.1-Gps Transceivers 12, 24
or 36
24 or 36 24, 36
or 48
24, 36
or 48
36 or 48 36 or 48 66 66 66 66
Fractional PLLs 20 24 28 28 28 28 24 24 32 32
M20K Memory Blocks 957 1,900 2,304 2,560 2,640 2,640 2,100 2,660 2,640 2,640
M20K Memory (Mbits) 19 37 45 50 52 52 41 52 52 52
Variable Precision
Multipliers (18x18)
512 512 512 512 704 704 798 798 704 704
Variable Precision
Multipliers (27x27)
256 256 256 256 352 352 399 399 352 352
DDR3 SDRAM x72
DIMM Interfaces
4 4 6 6 6 6 4 4 4 4

Altera Stratix® V GS High Bandwidth FPGAs

Altera's Stratix® V High Bandwidth FPGAs deliver the industry's highest bandwidth, highest level of system integration, and ultimate flexibility with reduced cost and the lowest total power for high-end applications. Advantages of the Stratix® V include the ability to attain breakthrough bandwidth with power-efficient transceivers, achieve higher integration on a single chip and reduce costs, get ultimate flexibility in your designs and lower your system power. Stratix® V GS FPGAs with enhanced digital signal processing (DSP) capabilities and transceivers offers to integrate up to 3,926 18x18, high-performance, variable-precision multipliers, 48 full-duplex, 14.1-Gbps transceivers , and up to 6 x72-bit DIMM DDR3 memory interfaces supporting 1,066 MHz. The GS variant is optimized for high-performance, variable-precision digital signal processing (DSP) applications with integrated transceivers supporting backplane, chip-to-chip, and chip-to-module operation at up to 14.1 Gbps.

Features
  • 28-nm TSMC process technology
  • Low-power serial transceivers
  • General-purpose I/Os (GPIOs)
  • Embedded HardCopy® Block
  • Embedded transceiver hard IP
  • Power Management
    • Programmable Power Technology
    • Quartus® II integrated PowerPlay Power Analysis
  • High-performance core fabric
  • Enhanced ALM with four registers
  • Embedded memory blocks
    • M20K: 20-Kbit with hard error correction code (ECC)
    • MLAB: 640-bit
  • Variable precision DSP blocks

    Fractional PLLs
  • Clock networks
    • 717-MHz fabric clocking
    • Global, quadrant, and peripheral clock networks
    • Device Configuration
    • Serial and parallel flash interface
    • Enhanced advanced encryption standard (AES) design
      security features
    • Tamper protection
    • Partial and dynamic reconfiguration
    • Configuration via Protocol (CvP)
  • High-performance packaging
  • HardCopy® V migration
Stratix® V  GS Family Features 
Feature 5SGSD3 5SGSD4 5SGSD5 5SGSD6 5SGSD8
Logic Elements (K) 236 360 457 583 695
Registers (K) 356 543 690 880 1,050
14.1-Gps Transceivers 12 or 24 12, 24 or 36 24 or 36 36 or 48 36 or 48
PCIe hard IP blocks 1 1 1 1, 2 or 4 1, 2 or 4
Fractional PLLs 20 20 24 28 28
M20K Memory Blocks 688 957 2,014 2,320 2,567
M20K Memory (Mbits) 13 19 39 45 50
Variable Precision Multipliers (18x18) 1,200 2,088 3,180 3,550 3,926
Variable Precision Multipliers (27x27) 600 1,044 1,590 1,775 1,963
DDR3 SDRAM x72 DIMM Interfaces 2 4 4 6 6

Altera Stratix® V GT High Bandwidth FPGAs

Altera's Stratix® V High Bandwidth FPGAs deliver the industry's highest bandwidth, highest level of system integration, and ultimate flexibility with reduced cost and the lowest total power for high-end applications. Advantages of the Stratix® V include the ability to attain breakthrough bandwidth with power-efficient transceivers, achieve higher integration on a single chip and reduce costs, get ultimate flexibility in your designs and lower your system power. Stratix® V GT FPGAs with transceivers offer to integrate four 28-Gbps transceivers and 32 full-duplex, 12.5-Gbps transceivers with up to 4 x72-bit DIMM DDR3 memory interfaces supporting 1,066 MHz. The GT variant is optimized for applications with 28.05 Gbps transceivers requiring ultra-high bandwidth and performance, such as 40G/100G/400G applications.

Features
  • 28-nm TSMC process technology
  • Low-power serial transceivers
  • General-purpose I/Os (GPIOs)
  • Embedded HardCopy® Block
  • Embedded transceiver hard IP
  • Power Management
    • Programmable Power Technology
    • Quartus II integrated PowerPlay Power Analysis
  • High-performance core fabric
  • Enhanced ALM with four registers
  • Embedded memory blocks
    • M20K: 20-Kbit with hard error correction code (ECC)
    • MLAB: 640-bit
  • Variable precision DSP blocks

  • Fractional PLLs
  • Clock networks
    • 717-MHz fabric clocking
    • Global, quadrant, and peripheral clock networks
  • Device Configuration
    • Serial and parallel flash interface
    • Enhanced advanced encryption standard (AES) design
      security features
    • Tamper protection
    • Partial and dynamic reconfiguration
    • Configuration via Protocol (CvP)
  • High-performance packaging
  • HardCopy® V migration
Stratix® V  GT Family Features 
Feature 5SGTC5 5SGTC7
Logic Elements (K) 425 622
Registers (K) 642 939
28.05/12.5-Gps Transceivers 4/32 4/32
PCIe hard IP blocks 1 1
Fractional PLLs 28 28
M20K Memory Blocks 2,304 2,560
M20K Memory (Mbits) 45 50
Variable Precision Multipliers (18x18) 512 512
Variable Precision Multipliers (27x27) 256 256
DDR3 SDRAM x72 DIMM Interfaces 4 4

Altera Stratix® V Development Tools


DSP Development Kit, Stratix® V Edition

Altera's DSP Development Kit, Stratix® V Edition, is a complete design environment that includes both the hardware and software you need to develop Stratix V GS FPGA designs. With this kit You can test Altera's optimized variable-precision digital signal processing (DSP) block, develop DSP algorithms in a high-level model-based flow, test signal quality of the FPGA transceiver I/Os (10 Gbps+), develop and test PCI Express® (PCIe) 3.0 designs, develop and test memory subsystems consisting of SyncFlash, DDR3, and QDRII+, develop and test SDI with the embedded 75-ohm 3G SDI transceivers, develop embedded designs utilizing the Nios® II processor and external memory, develop and test network designs utilizing Triple Speed Ethernet MegaCore® and external RJ-45 jack, develop and test optical networking designs using the 10-Gbps and 40-Gbps ethernet MAC MegaCores and the QSFP Optical Interface, measure the FPGA's power consumption, and control twelve different programmable clock oscillators using the Clock Control GUI.



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Stratix® V GX FPGA Development Kit

Altera's Stratix® V GX FPGA Development Kit is a complete design environment that includes both the hardware and software you need to develop Stratix V GX FPGA designs. With this kit you can test signal quality of the FPGA transceiver I/Os (10 Gbps+), develop and test PCI Express® (PCIe) 3.0 designs, develop and test memory subsystems consisting of SyncFlash, DDR3, and QDRII+, develop and test SDI with the embedded 75-ohm 3G SDI transceivers, develop embedded designs utilizing the Nios® II processor and external memory, develop and test network designs utilizing Triple Speed Ethernet MegaCore® and external RJ-45 jack, develop and test optical networking designs using the 10G and 40G Ethernet MAC MegaCores and the QSFP Optical Interface, measure the FPGA's power consumption, and control twelve different programmable clock oscillators using the Clock Control GUI.


100G Development Kit, Stratix® V GX Edition

Altera's Stratix® V GX 100G Development Kits are a complete design environment that includes both the hardware and software you need to develop Stratix V GX FPGA designs. With this kit you can support 10G/40G and 100G line interfaces through optical modules, support applications requiring external memory interfaces, through 6x32-bit DDR3 and 1x36- and 1x18-bit QDRII BL2 memory banks, use system-side interfaces via two pairs of FCI AirMax connectors, complete line-side (optical modules) to system-side (AirMax connector) datapath analysis, evaluate transceiver performance up to 12.5 Gbps, verify physical medium attachment (PMA) compliance to 10G/40G/100G Ethernet, Interlaken, CEI-6G/11G, and other major standards, and validate interoperability between optical modules, such as SFP, SFP+, QSFP, and CFP.


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Stratix® V GX Transceiver Signal Integrity Development Kit

The Altera® Stratix® V GX Transceiver Signal Integrity Development Kits are a complete design environment that includes both the hardware and software you need to develop Stratix V GX FPGA designs. The one-year license for the Quartus® II software provides everything you need to begin developing custom Stratix V GX FPGA designs. With this kit you can evaluate transceiver performance from 600 Mbps up to 12.5 Gbps, generate and check pseudo-random binary sequence (PRBS) patterns, dynamically change differential output voltage (VOD) pre-emphasis, and equalization settings to optimize transceiver performance for your channel, perform jitter analysis, and verify physical medium attachment (PMA) compliance to PCI Express®(PCIe®), Gbps Ethernet (GbE), XAUI, CEI-6G, Serial RapidIO®, high-definition serial digital interface (HD-SDI), and other major standards.


Stratix® V GT Transceiver Signal Integrity Development Kit

Altera's Stratix® V GT Transceiver Signal Integrity Development Kit is a complete design environment that includes both the hardware and software you need to develop Stratix V GT FPGA designs. The one-year license for the Quartus® II software provides everything you need to begin developing custom Stratix V GT FPGA designs. With this kit you can evaluate transceiver performance from 600 Mbps up to 12.5 Mbps, evaluate transceiver performance up to 25 Gbps for the GT channels, generate and check pseudo-random binary sequence (PRBS) patterns, dynamically change differential output voltage (VOD) pre-emphasis, and equalization settings to optimize transceiver performance for your channel, perform jitter analysis, verify physical medium attachment (PMA) compliance to PCI Express®(PCIe®), Gbps Ethernet (GbE), XAUI, CEI-6G, Serial RapidIO®, high-definition serial digital interface (HD-SDI), and other major standards.



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Cypress Sync SRAM

Cypress Synchronous SRAM offers true random memory access capabilities required for networking and other high performance applications. The Cypress Synchronous SRAM portfolio is available with a number of features designed to solve networking and high performance computing challenges. The portfolio includes standard synchronous SRAM, No Bus Latency SRAM, and QDR® SRAM with a variety of speeds, word widths, densities, and packages. 

Cypress Synchronous SRAM devices are ideal for a wide range of applications including high-speed network switches & routers, communications infrastructure, test equipment, imaging & video and high performance computing.



Standard Sync NoBL™
No Bus Latency
QDR® - II /
DDR-II
QDR - II+ /
DDR-II+
QDR - II+X /
DDR-II+X

Max RTR1: 250MT/s
Max BW:18Gbps
Latency: 1 Cycle
Pipeline and Flow-through Mode

Max RTR1: 250MT/s
Max BW: 18Gbps
Latency: 1 Cycle
Pipeline and Flow-through Mode
Max RTR1: 666MT/s
Max BW: 47.9Gbps
Latency: 1.5 Cycles
CIO2 and SIO3
Max RTR1: 666MT/s
Max BW: 79.2Gbps
Latency: 2 or
2.5 Cycles
CIO2 and SIO3, ODT4
Max RTR1: 900MT/s
Max BW: 91.1Gbps
Latency: 2.5 Cycles
SIO3, ODT4

Density
    CY7C161/2xKV18
144 Mb; 250-333 MHz
1.8 V; x9, x18, x36
Burst 2, 4
CY7Cx4/5/6/7xKV18
144 Mb; 300-550 MHz
1.8 V; x18, x36
Burst 2, 4
 
CY7C148xB
72 Mb; 133-250 MHz
2.5, 3.3 V; x18, x36

CY7C147x
72 Mb; 133-250 MHz
2.5, 3.3V; x18, x36
CY7C151/2xKV18
72 Mb; 250-333 MHz
1.8 V; x9, x18, x36
Burst 2, 4
CY7Cx54/5/6/7xKV18
72 Mb; 250-550 MHz
1.8 V; x18, x36
RH6; Burst 2, 4
CY7C40xKV12
72 Mb; 667-1066 MHz
1.25 V; x18, x36
Burst 2
CY7C144xA
36 Mb; 133-250 MHz
2.5, 3.3 V; x36, x72
 
CY7C146x
36 Mb; 133-250 MHz
2.5, 3.3V; x18, x36
CY7C141/2xKV18
36 Mb; 250-333 MHz
1.8 V; x8, x9, x18, x36
Burst 2, 4
CY7Cx24/5/6/7xKV18
36 Mb; 400-550 MHz
1.8 V; x18, x36
Burst 2, 4
CY7C126/7x
36 Mb; 366-633 MHz
1.8 V; x18, x36
Burst 2, 4
CY7C138xD
18 Mb; 100-250 MHz
3.3 V; x18, x32, x36
CY7C137xD
18 Mb; 100-250 MHz
2.5, 3.3V x18, x32, x36
CY7C131/2/9xKV18
18 Mb; 250-333 MHz
1.8 V; x8, x18, x36
Burst 2, 4
CY7Cx14/5/6/7xKV18
18 Mb; 400-550 MHz
1.8 V; x18, x36
Burst 2, 4
 
CY7C136xC
9 Mb; 100-250 MHz
3.3 V; x18, x32, x36
Auto
5
CY7C135xC
9 Mb; 100-250 MHz
2.5, 3.3 V; x18, x36
CY7C1911xKV18
18 Mb; 250-333 MHz
1.8 V; x9
Burst 2, 4
   
CY7C134/2xG
2, 4 Mb; 100-250 MHz
3.3 V; x18, x32, x36
 
 CY7C135xG
4 Mb; 100-200 MHz
3.3 V; x18, x36
     
 Learn More About Standard Sync
 Learn More About NoBL Sync SRAM Learn More About QDR-II DDR-II Sync SRAM  Learn More About QDR-II+ DDR-II+ Sync SRAM Learn More About QDR-II+Xtreme DDR-II+ Xtreme Sync SRAM  
      Random Transaction Rate

1 Rate of truly random accesses   to memory expressed in transactions per second (MT/s) 
2 Common I/O
3 Separate I/O  
4 On-die termination; parts are CY7C2x 
5 AEC-Q100 −40ºC to +125ºC 
6 Radiation hardened, military grade −55ºC to +125ºC
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