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Home » NEWEST Products » New by Manufacturer » Altera Corporation » Altera Stratix IV High Density High Performance FPGAs
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Altera Stratix IV High Density High-Performance FPGAs

Altera Stratix® IV High Density High-Performance FPGAs

Altera's Stratix® IV High Density High Performance FPGAs deliver a breakthrough level of system bandwidth and power efficiency for high-end applications, allowing you to innovate without compromise. The Stratix IV device family contains three optimized variants to meet different application requirements.

Altera Stratix® IV E (Enhanced) High Density High-Performance FPGAs

Altera's Stratix® IV High Density High Performance FPGAs deliver a breakthrough level of system bandwidth and power efficiency for high-end applications, allowing you to innovate without compromise. The Stratix IV E (Enhanced) FPGAs—up to 813,050 logic elements (LEs), 33,294 kilobits (Kb) RAM, and 1,288 18 x 18 bit multipliers. Stratix IV E devices provide an excellent solution for applications that do not require high-speed CDR-based transceivers, but are logic, user I/O, or memory intensive.

Features
  • Dedicated circuitry to support physical layer functionality for
    popular serial protocols, such as PCI Express (PCIe) (PIPE) Gen1 and Gen2, Gbps Ethernet (GbE), Serial RapidIO, SONET/SDH, XAUI/HiGig, (OIF) CEI-6G, SD/HD/3G-SDI, Fibre Channel, SFI-5, and Interlaken
  • Complete PCIe protocol solution with embedded PCIe hard IP blocks that implement PHY-MAC layer, Data Link layer, and Transaction layer functionality
  • Programmable transmitter pre-emphasis and receiver equalization circuitry to compensate for frequency-dependent losses in the physical medium
  • Typical physical medium attachment (PMA) power consumption of 100 mW at 3.125 Gbps and 135 mW at 6.375 Gbps per channel
  • 72,600 to 813,050 equivalent LEs per device
  • 7,370 to 33,294 Kb of enhanced TriMatrix memory consisting of three RAM block sizes to implement true dual-port memory and FIFO buffers
  • High-speed digital signal processing (DSP) blocks configurable as 9 x 9-bit, 12 x 12-bit, 18 x 18-bit, and 36 x 36-bit full-precision multipliers at up to 600 MHz

  • Up to 16 global clocks (GCLK), 88 regional clocks (RCLK), and 132 periphery clocks (PCLK) per device
  • Programmable power technology that minimizes power while maximizing device performance
  • Up to 1,120 user I/O pins arranged in 24 modular I/O banks that support a wide range of single-ended and differential I/O standards
  • Support for high-speed external memory interfaces including DDR, DDR2, DDR3 SDRAM, RLDRAM II, QDR II, and QDR II+ SRAM on up to 24 modular I/O banks
  • High-speed LVDS I/O support with serializer/deserializer (SERDES), dynamic phase alignment (DPA), and soft-CDR circuitry at data rates up to 1.6 Gbps
  • Support for source-synchronous bus standards, including SGMII, GbE, SPI-4 Phase 2 (POS-PHY Level 4), SFI-4.1, XSBI, UTOPIA IV, NPSI, and CSIX-L1
  • Pinouts for Stratix IV E devices designed to allow migration of designs from Stratix III to Stratix IV E with minimal PCB impact
Stratix® IV  E Family Features
Feature EP4SE230 EP4SE360 EP4SE530 EP4SE820
Package Pin Count 780
780
1152
1152
1517
1760
1152
1517
1760
ALMs 91,200 141,440 212,480 325,220
LEs 228,000 353,600 531,200 813,050
High-Speed LVDS
SERDES (up to
1.6 Gbps)
56 56 88 88 112 112 88 112 132
SPI-4.2 Links 3 3 4 4 6 6 4 6 6
M9K Blocks
(256 x 36 bits)
1,235 1,248 1,280 1,610
M144K Blocks
(2048 x 72 bits)
22 48 64 60
Total Memory
(MLAB+M9K+
M144K) Kb
17,133 22,564 27,376 33,294
Embedded Multipliers
(18 x 18)
1,288 1,040 1,024 960
PLLs 4 4 8 8 12 12 8 12 12
User I/Os 488 488 744 744 976 976 744 976 1,120

Altera Stratix® IV GX High Density High-Performance FPGAs

Altera's Stratix® IV High Density High Performance FPGAs deliver a breakthrough level of system bandwidth and power efficiency for high-end applications, allowing you to innovate without compromise. The Stratix® IV GX transceiver FPGAs—up to 531,200 LEs, 27,376 Kb RAM, 1,288 18 x 18-bit multipliers. These devices provide up to 48 full-duplex CDR-based transceiver channels per device. Thirty-two out of the 48 transceiver channels have dedicated physical coding sublayer (PCS) and physical medium attachment (PMA) circuitry and support data rates between 600 Mbps and 8.5 Gbps. The remaining 16 transceiver channels have dedicated PMA-only circuitry and support data rates between 600 Mbps and 6.5 Gbps

Features
  • Up to 48 full-duplex CDR-based transceivers support data rates up to 8.5 Gbps and 11.3 Gbps, respectively
  • Dedicated circuitry to support physical layer functionality for popular serial protocols, such as PCI Express (PCIe) (PIPE) Gen1 and Gen2, Gbps Ethernet (GbE), Serial RapidIO, SONET/SDH, XAUI/HiGig, (OIF) CEI-6G, SD/HD/3G-SDI, Fibre Channel, SFI-5, and Interlaken
  • Complete PCIe protocol solution with embedded PCIe hard IP blocks that implement PHY-MAC layer, Data Link layer, and Transaction layer functionality
  • Programmable transmitter pre-emphasis and receiver equalization circuitry to compensate for frequency-dependent losses in the physical medium
  • Typical physical medium attachment (PMA) power consumption of 100 mW at 3.125 Gbps and 135 mW at 6.375 Gbps per channel
  • 72,600 to 813,050 equivalent LEs per device
  • 7,370 to 33,294 Kb of enhanced TriMatrix™ memory consisting of three RAM block sizes to implement true dual-port memory and FIFO buffers
  • High-speed digital signal processing (DSP) blocks configurable as 9 x 9-bit, 12 x 12-bit, 18 x 18-bit, and 36 x 36-bit full-precision multipliers at up to 600 MHz

  • Up to 16 global clocks (GCLK), 88 regional clocks (RCLK), and 132 periphery clocks (PCLK) per device
  • Programmable power technology that minimizes power while maximizing device performance
  • Up to 1,120 user I/O pins arranged in 24 modular I/O banks that support a wide range of single-ended and differential I/O standards
  • Support for high-speed external memory interfaces including DDR, DDR2, DDR3 SDRAM, RLDRAM II, QDR II, and QDR II+ SRAM on up to 24 modular I/O banks
  • High-speed LVDS I/O support with serializer/deserializer (SERDES), dynamic phase alignment (DPA), and soft-CDR circuitry at data rates up to 1.6 Gbps
  • Support for source-synchronous bus standards, including SGMII, GbE, SPI-4 Phase 2 (POS-PHY Level 4), SFI-4.1, XSBI, UTOPIA IV, NPSI, and CSIX-L1
 
Stratix® IV  GX Family Features 
Feature EP4SGX70 EP4SGX110 EP4SGX180 EP4SGX230
Package Pin Count 780 1152 780 1152 780 1152 1517 780 1152
1517
ALMs 29,040 42,240 70,300 91,200
LEs 72,600 105,600 175,750 228,000
High-Speed LVDS
SERDES (up to 1.6 Gbps)
28 56 28 56 28 44 88 28 44 88
SPI-4.2 Links 1 1
1 2 4 1 2 4
M9K Blocks
(256 x 36 bits)
462 660 950 1,235
M144K Blocks
(2048 x 72 bits)
16 16 20 22
Total Memory
(MLAB+M9K+ M144K) Kb
7,370 9,564 13,627 17,133
Embedded Multipliers
(18 x 18)
384 512 920 1288
PLLs 3 4 3 4 3
6 8 3 6 8
User I/Os 372 488 372 372 488 372 564 564 744 372 564 564 744

Feature EP4SGX290 EP4SGX360 EP4SGX530
Package Pin Count 780 1152 1517 1760 1932 780 1152 1517 1760 1932 1760
1932
ALMs 116,480 141,440 212,480
LEs 291,200 353,600 531,200
High-Speed LVDS
SERDES (up to
1.6 Gbps)
- 44 88 98 - 44 88 98 88 98
SPI-4.2 Links - 2 2 4 4 4 - 2 2 4 4 4 4 4
M9K Blocks
(256 x 36 bits)
936 1,248 1,280
M144K Blocks
(2048 x 72 bits)
36 48
64
Total Memory
(MLAB+M9K+
M144K) Kb
17,248 22,564 27,376
Embedded Multipliers
(18 x 18)
832 1,040 1,024 1,024
PLLs 4 6 8 12 12 4 6 8 12 12 12 12
User I/Os 289 564 564 744 880 920 289 564 564 744 880 920 880 920


Altera Stratix® IV GT High Density High-Performance FPGAs

Altera's Stratix® IV High Density High Performance FPGAs deliver a breakthrough level of system bandwidth and power efficiency for high-end applications, allowing you to innovate without compromise. The Stratix® IV GT—up to 531,200 LEs, 27,376 Kb RAM, 1,288 18 x 18-bit multipliers, and 48 full-duplex CDR-based transceivers at up to 11.3 Gbps. Stratix® IV GT devices provide up to 48 CDR-based transceiver channels per device. Thirty-two out of the 48 transceiver channels have dedicated PCS and PMA circuitry and support data rates between 600 Mbps and 11.3 Gbps. The remaining 16 transceiver channels have dedicated PMA-only circuitry and support data rates between 600 Mbps and 6.5 Gbps.

Features
  • Up to 48 full-duplex CDR-based transceivers in Stratix IV GT devices support data rates up to 8.5 Gbps and 11.3 Gbps, respectively
  • Dedicated circuitry to support physical layer functionality for popular serial protocols, such as PCI Express (PCIe) (PIPE) Gen1 and Gen2, Gbps Ethernet (GbE), Serial RapidIO, SONET/SDH, XAUI/HiGig, (OIF) CEI-6G, SD/HD/3G-SDI, Fibre Channel, SFI-5, and Interlaken
  • Complete PCIe protocol solution with embedded PCIe hard IP blocks that implement PHY-MAC layer, Data Link layer, and Transaction layer functionality
  • Programmable transmitter pre-emphasis and receiver equalization circuitry to compensate for frequency-dependent losses in the physical medium
  • Typical physical medium attachment (PMA) power consumption of 100 mW at 3.125 Gbps and 135 mW at 6.375 Gbps per channel
  • 72,600 to 813,050 equivalent LEs per device
  • 7,370 to 33,294 Kb of enhanced TriMatrix™ memory consisting of three RAM block sizes to implement true dual-port memory and FIFO buffers
  • High-speed digital signal processing (DSP) blocks configurable as 9 x 9-bit, 12 x 12-bit, 18 x 18-bit, and 36 x 36-bit full-precision multipliers at up to 600 MHz

  • Up to 16 global clocks (GCLK), 88 regional clocks (RCLK), and 132 periphery clocks (PCLK) per device
  • Programmable power technology that minimizes power while maximizing device performance
  • Up to 1,120 user I/O pins arranged in 24 modular I/O banks that support a wide range of single-ended and differential I/O standards
  • Support for high-speed external memory interfaces including DDR, DDR2, DDR3 SDRAM, RLDRAM II, QDR II, and QDR II+ SRAM on up to 24 modular I/O banks
  • High-speed LVDS I/O support with serializer/deserializer (SERDES), dynamic phase alignment (DPA), and soft-CDR circuitry at data rates up to 1.6 Gbps
  • Support for source-synchronous bus standards, including SGMII, GbE, SPI-4 Phase 2 (POS-PHY Level 4), SFI-4.1, XSBI, UTOPIA IV, NPSI, and CSIX-L1
 
Stratix® IV  GT Family Features 
Feature EP4S40G2 EP4S40G5 EP4S100G2 EP4S100G3 EP4S100G4 EP4S100G5
Package Pin Count 1517
1517
1517
1932
1932
1517
1932
ALMs 91,200 212,480 91,200 116,480 141,440 212,480
LEs 228,000 531,200 228,000 291,200 353,600 531,200
Total Transceiver
Channels
36 36 36 48 48 36 48
High-Speed LVDS
SERDES (up to
1.6 Gbps)
46 46 46 47 47 46 47
SPI-4.2 Links 2 2 2 2 2 2 2
M9K Blocks
(256 x 36 bits)
1,235 1,280 1,235 936 1,248 1,280
M144K Blocks
(2048 x 72 bits)
22 64 22 36 48 64
Total Memory
(MLAB+M9K+
M144K) Kb
17,133 27,376 17,133 17,248 22,564 27,376
Embedded Multipliers
(18 x 18)
1,288 1,040 1,288 832 1,024 1,024
PLLs 8 8 8 12 12 8 12
User I/Os 654 654 654 781 781 654 781

Altera Stratix® IV Development Tools

  View Product List

Stratix® IV GX Audio Video Development Kit

Altera's Audio Video Development Kit, Stratix® IV GX Edition is a complete design environment that includes both the hardware and software you need to develop Stratix IV GX FPGA designs. The PCI-SIG-compliant board, the serial digital interface (SDI) high-speed mezzanine card (HSMC), and the one-year license for the Quartus® II software provide everything you need to begin developing custom Stratix IV GX FPGA designs. With this kit you can develop and test PCI Express 2.0 designs, develop and test memory subsystems consisting of DDR3 and QDR II+ memories, build designs capable of migrating to Altera’s low-cost HardCopy® IV ASICs, and develop and test SDI and Audio Engineering Society (AES) designs using the SDI HSMC in conjunction with the host development platform.


Stratix® IV GX FPGA Development Kits

Altera's Stratix® IV GX FPGA Development Kits are a complete design environment that includes both the hardware and software you need to develop Stratix IV GX FPGA designs. The PCI-SIG-compliant board and the one-year license for the Quartus® II software provide everything you need to begin developing custom Stratix IV GX FPGA designs. With these kits you can develop and test PCI Express® (PCIe) 2.0 designs, develop and test memory subsystems consisting of DDR3 and QDR II+ memories, build designs capable of migrating to Altera’s low-cost HardCopy® IV ASICs, develop FPGA designs for cost-sensitive applications, and measure the FPGA's power consumption.



View Product List



View Product List

Stratix® IV GX Edition Transceiver Signal Integrity Development Kit

Altera's Transceiver Signal Integrity Development Kit, Stratix® IV GX Edition provides everything you need for the signal integrity evaluation and interoperability of Stratix IV GX transceivers on the Altera® Stratix IV GX EP4SGX230 device. The kit includes a full-featured FPGA development board, hardware and software evaluation tools, documentation, and accessories needed to begin development. With this signal integrity development kit, you can evaluate transceiver performance at data rate ranging from 600 Mbps to 8.5 Gbps, generate and check pseudo-random binary sequence (PRBS) patterns through an easy-to-use demonstration application, understand the effects of changing differential output voltage (VOD), preemphasis, and equalization settings, perform jitter analysis, and verify physical medium attachment (PMA) compliance to PCI Express (Gen 1 and Gen 2), Serial RapidIO®, gigabit Ethernet, 10 gigabit Ethernet XAUI, CEI-6G, high definition serial digital interface (HD-SDI), Fibre Channel 1G/4G/8G, and other major standards.


Stratix® IV GT 100G Development Kit

Altera's Stratix® IV GT 100G Development Kit is a complete design environment that includes both the hardware and software you need to develop Stratix IV GT FPGA designs. With this kit you will be able to test signal quality of the FPGA transceiver I/Os (up to 11.3 Gbps), develop and test optical networking interfaces such as CFP, quad small-formfactor pluggable (QSFP), and small form-factor Pluggable (SFP+) interface, develop embedded designs utilizing the Nios® II processor and the SSRAM memory, develop and test network designs utilizing the Gigabit Ethernet PHY and the FPGA transceivers, develop FPGA designs for high-performance applications, and measure the FPGA's power consumption.

View Product List


View Product List

Stratix® IV GT Transceiver Signal Integrity Development Kit

Altera's Transceiver Signal Integrity Development Kit, Stratix® IV GT Edition provides everything you need for the signal integrity evaluation and interoperability of Stratix® IV GT transceivers on the Altera® Stratix® IV GT EP4S100G2 device. The kit includes a full-featured FPGA development board, hardware and software evaluation tools, documentation, and accessories needed to begin development. This kit allows you to evaluate transceiver performance at data rates up to 11.3 Gbps, generate and check pseudo-random binary sequence (PRBS) patterns through an easy-to-use demonstration application, understand the effects of changing differential output voltage (VOD), preemphasis, and equalization settings, perform jitter analysis, and verify physical medium attachment (PMA) compliance to 10 gigabit Ethernet, Interlaken, 10G GPON/EPON, IEEE 802.3ba 40G, SONET OC-192, and other major standards.

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