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Home » NEWEST Products » New by Manufacturer » Altera Corporation » Stratix & GX High-End FPGAs - Altera
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Altera Stratix & Stratix GX High-End FPGAs

Altera Stratix® & GX High-End FPGAs

The Stratix® FPGA family, Altera's first generation of high-end FPGA families, combined an architecture tuned for high performance with the highest level of integration available on an FPGA from any vendor. A Stratix® FPGA can provide up to 80K logic elements (LEs) and 7.3 Mbits of on-chip RAM arranged in TriMatrix memory blocks, operating at up to 350 MHz. The Stratix® FPGA supports external memory interfaces such as DDR SDRAM at 400 Mbps and QDRII SRAM at 800 Mbps. The Stratix® FPGA also introduced the world's first digital signal processing (DSP) block, containing four 18 x 18 multipliers, accumulators, and a summation unit. Building on the Stratix® FPGA high-performance architectural features, the Stratix® GX FPGA is the first programmable logic device to incorporate high-speed serial transceivers operating at multi-gigabit speeds. Using a transceiver block supporting four full-duplex channels and clock data recovery (CDR) technology allows transmission of data in excess of 3.1875-Gbps per channel.

Stratix® High-End FPGA Family

The Stratix® FPGA family is the first-generation of Altera's Stratix® FPGA series. For most applications, this FPGA generation is superseded by the award winning 90-nm Stratix® II family and Altera's leading edge 65-nm Stratix III and 40-nm Stratix® IV FPGA generations. These newer FPGA families offer features found in previous generations of the Stratix® FPGA series, including high-performance architecture, digital signal processing (DSP) blocks, external memory device interface, TriMatrix™ memory, differential I/O standards, and high-speed interfaces.


Additional Resources
Stratix® Datasheet
Altera Stratix & Stratix GX High-End FPGAs

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Features
  • 10,570 to 79,040 LEs
  • Up to 7,427,520 RAM bits (928,440 bytes) available without reducing logic resources
  • TriMatrix™ memory consisting of three RAM block sizes to implement true dual-port memory and first-in first-out (FIFO) buffers
  • High-speed DSP blocks provide dedicated implementation of multipliers (faster than 300 MHz), multiply-accumulate functions, and finite impulse response (FIR) filters
  • Up to 16 global clocks with 22 clocking resources per device region
  • Up to 12 PLLs (four enhanced PLLs and eight fast PLLs) per device provide spread spectrum, programmable bandwidth, clock switchover, real-time PLL reconfiguration, and advanced multiplication and phase shifting
  • Support for numerous single-ended and differential I/O standards
  • High-speed differential I/O support on up to 116 channels with up to 80 channels optimized for 840 megabits per second (Mbps)

  • Support for high-speed networking and communications bus standards including RapidIO, UTOPIA IV, CSIX, HyperTransportTM technology, 10G Ethernet XSBI, SPI-4 Phase 2 (POS-PHY Level 4), and SFI-4
  • Differential on-chip termination support for LVDS
  • Support for high-speed external memory, including zero bus turnaround (ZBT) SRAM, quad data rate (QDR and QDRII) SRAM, double data rate (DDR) SDRAM, DDR fast cycle RAM (FCRAM), and single data rate (SDR) SDRAM
  • Support for 66-MHz PCI (64 and 32 bit) in -6 and faster speed-grade devices, support for 33-MHz PCI (64 and 32 bit) in -8 and faster speed-grade devices
  • Support for 133-MHz PCI-X 1.0 in -5 speed-grade devices
  • Support for 100-MHz PCI-X 1.0 in -6 and faster speed-grade devices
  • Support for 66-MHz PCI-X 1.0 in -7 speed-grade devices
  • Support for multiple intellectual property megafunctions from Altera MegaCore® functions and Altera Megafunction Partners Program (AMPPSM) megafunctions
  • Support for remote configuration updates
Stratix Device Features
Feature EP1S10 EP1S20 EP1S25 EP1S30 EP1S40 EP1S60 EP1S180
LEs 10,570 18,460 25,660 32,470 41,250 57,120 79,040
M512 RAM blocks (32x18 bits) 94 194 224 295 384 574 767
M4K RAM blocks (128x36 bits) 60 82 138 171 183 292 364
M-RAM blocks (4Kx144 bits) 1 2 2 4 4 6 9
Total RAM bits 920,448 1,669,248 1,944,576 3,317,184 3,423,744 5,215,104 7,427,520
DSP blocks 6 10 10 12 14 18 22
Embedded multipliers 48 80 80 96 112 144 176
PLLs 6 6 6 10 12 12 12
Max. user I/O pins 426 586 706 726 822 1022 1238

Stratix® GX High-End FPGA Family

Stratix® GX FPGAs give system architects a low-risk path to 3.125-Gbps transceiver applications. Based on Altera's Stratix® architecture, Stratix® GX devices fuse the industry's fastest FPGA architecture with high-performance multi-gigabit transceiver technology. System designs that require a low-risk cost-reduction path for high-volume production can migrate Stratix® GX designs seamlessly to mask-programmed, pin-compatible HardCopy® Stratix® GX devices. Because HardCopy Stratix® GX devices preserve the high-density, high-performance architecture of Stratix® GX FPGAs, including the 3.125-Gbps high-speed transceivers, no additional high-speed board design engineering is required when migrating from Stratix® GX FPGAs to HardCopy Stratix® GX devices.


Additional Resources
Stratix GX Datasheet


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FPGA Features
  • 10,570 to 41,250 logic elements (LEs)
  • Up to 3,423,744 RAM bits (427,968 bytes) available without
    reducing logic resources
  • TriMatrix™ memory consisting of three RAM block sizes to
    implement true dual-port memory and first-in-out (FIFO) buffers
  • Up to 16 global clock networks with up to 22 regional clock
    networks per device region
  • High-speed DSP blocks provide dedicated implementation of
    multipliers (faster than 300 MHz), multiply-accumulate functions, and finite impulse response (FIR) filters
  • Up to eight general usage phase-locked loops (four enhanced
    PLLs and four fast PLLs) per device provide spread spectrum, programmable bandwidth, clock switchover, real-time PLL reconfiguration, and advanced multiplication and phase shifting
  • Support for numerous single-ended and differential I/O standards
    High-speed source-synchronous differential I/O support on up
    to 45 channels for 1-Gbps performance
  • Support for source-synchronous bus standards, including
    10-Gigabit Ethernet XSBI, Parallel RapidIO, UTOPIA IV,
    Network Packet Streaming Interface (NPSI), HyperTransport™
    technology, SPI-4 Phase 2 (POS-PHY Level 4), and SFI-4
  • Support for high-speed external memory, including zero bus turnaround (ZBT) SRAM, quad data rate (QDR and QDRII)
    SRAM, double data rate (DDR) SDRAM, DDR fast cycle RAM (FCRAM), and single data rate (SDR) SDRAM
  • Support for multiple intellectual property megafunctions from Altera® MegaCore® functions and Altera Megafunction
    Partners Program (AMPPSM) megafunctions
  • Support for remote configuration updates
  • Dynamic phase alignment on LVDS receiver channels
Transceiver Features
  • High-speed serial transceiver channels with CDR provides 500-megabits per second (Mbps) to 3.1875-Gbps full-duplex operation
  • Devices are available with 4, 8, 16, or 20 high-speed serial transceiver channels providing up to 127.5 Gbps of full-duplex serial bandwidth
  • Support for transceiver-based protocols, including 10 Gigabit Ethernet attachment unit interface (XAUI), Gigabit Ethernet (GigE), and SONET/SDH
    Compatible with PCI Express, SMPTE 292M, Fibre Channel, and Serial RapidIO I/O standards
  • Programmable differential output voltage (VOD), pre-emphasis, and equalization settings for improved signal integrity
  • Individual transmitter and receiver channel power-down capability implemented automatically by the Quartus® II software for reduced power consumption during non-operation
  • Programmable transceiver-to-FPGA interface with support for 8-, 10-, 16-, and 20-bit wide data paths
    1.5-V pseudo current mode logic (PCML) for 500 Mbps to 3.1875 Gbps
  • Support for LVDS, LVPECL, and 3.3-V PCML on reference clocks and receiver input pins (AC-coupled)
  • Built-in self test (BIST)
  • Hot insertion/removal protection circuitry
  • Pattern detector and word aligner supports programmable patterns
  • 8B/10B encoder/decoder performs 8- to 10-bit encoding and 10-to 8-bit decoding
  • Rate matcher compliant with IEEE 802.3-2002 for GigE mode and with IEEE 802-3ae for XAUI mode
  • Channel bonding compliant with IEEE 802.3ae (for XAUI mode only)
  • Device can bypass some transceiver block features if necessary
Stratix GX Device Features


Feature

EP1SGX10C
EP1SGX10D
EP1SGX25C
EP1SGX25D
EP1SGX25F

EP1SGX40D
EP1SGX40G
LEs 10,570 25,660 41,250
Transceiver channels 4, 8 4, 8, 16 8, 20
Source-synchronous channels 22 39 45
M512 RAM blocks (32x18 bits) 94 224 384
M4K RAM blocks (128x36 bits) 60 138 183
M-RAM blocks (4Kx144 bits) 1 2 4
Total RAM bits 920,448 1,944,576 3,423,744
Digital signal processing (DSP) blocks 6 10 14
Embedded multipliers 48 80 112
PLLs 4 4 8
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