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Home » NEWEST Products » New by Manufacturer » Altera Corporation » FPGA SoC Family - Altera
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Altera SoC FPGA Family

Altera SoC FPGA Family

Altera SoC FPGA Overview


Altera SoC FPGAs

Altera SoCs integrate an ARM-based hard processor system (HPS) consisting of processor, peripherals, and memory interfaces with the FPGA fabric using a high-bandwidth interconnect backbone. They combine the performance and power savings of hard intellectual property (IP) with the flexibility of programmable logic. These user-customizable ARM-based SoCs are ideal for reducing system power, cost, and board size by integrating discrete processors and digital signal processing (DSP) functions into a single FPGA. They differentiate the end product with custom hardware and software and add support for virtually any interface standard or protocol in the FPGA.

Altera's SoCs extend product life and revenue through hardware and software updates in the field. They also improve system performance via high-bandwidth interconnect between the processor and the FPGA. These devices join the diverse family of Cyclone® V and Arria® V with dozens of devices and variations and include additional hard logic such as PCI Express® Gen2, multiport memory controllers, and high-speed serial transceivers. Built on TSMC's 28nm Low-Power (28LP) process, the SoCs drive down power and cost while enabling performance levels required by cost-sensitive applications.

Learn More About Altera's SoC Embedded Design Suite

Features
Processor Architecture
  • Dual-core ARM Cortex-A9 MPCore processor
    • Up to 800MHz maximum frequency
    • Support for symmetric multiprocessing (SMP) and asymmetric multiprocessing (AMP)
  • Each processor core includes:
    • 32KB of L1 instruction cache
    • 32KB of L1 data cache
    • NEON media processing engine
    • Single- or double-precision floating-point unit
    • Memory management unit (MMU)
    • Private interval timer
    • Private watchdog timer
    • 512KB of shared level 2 (L2) cache
  • SCU for cache coherency
  • Accelerator coherency port (ACP)
  • Global timer
  • Generic interrupt controller
  • CoreSight™ instruction trace
Memory Interface Support
  • Multiport SDRAM controller subsystem
    • DDR2 and DDR3
    • LPDDR1 and LPDDR2
    • Error correction code (ECC)
  • Flash memory controller
    • NAND with direct memory access (DMA)
      and optional ECC
    • Quad SPI (NOR)
    • Secure Digital (SD)/ secure digital I/O
      (SDIO)/ MultiMediaCard (MMC) with DMA
Interface Peripherals
  • Two 10/100/1000Mbps Ethernet media access controllers (EMACs) with DMA
  • Two USB 2.0 On-The-Go (USB OTG) controllers with DMA
  • Four I²C controllers
  • Two controller area networks (CAN), two master SPIs, two slave SPIs, UART
  • Up to 71 general-purpose I/Os (GPIOs)
    and 14 input-only
Debug
  • IEEE standard 1149.1-2001 (JTAG)
    • CPU Debug Access Port (DAP)
    • Direct memory debug via Advanced High-performance Bus Access Port (AHB-AP)
  • Embedded trace router (ETR) port with DMA
    • Processor trace
    • System bus trace
    • Operating system (OS) trace
  • On-chip trace storage
Hard Processor System

Hard Processor System

System Peripherals
  • Four general purpose timers
  • Two watchdog timers
  • 8-channel DMA controller
  • FPGA manager for FPGA configuration
  • Clock and reset managers
On-Chip Memory
  • 64KB on-chip RAM
  • 64KB on-chip boot ROM
HPS/FPGA Interfaces
  • HPS-to-FPGA bridges
    • Processor and DMA access to FPGA peripherals
    • Configurable 32-, 64-, or 128-bit Advanced Microcontroller Bus Architecture (AMBA®) Advanced eXtensible Interface (AXI™)
  • FPGA-to-HPS bridges
    • FPGA masters access processor subsystem peripherals
    • Configurable 32-, 64-, or 128-bit AMBA AXI interface
    • Coherent access to processor cache through ACP
    • FPGA-to-HPS SDRAM controller subsystem interface
    • FPGA access to DRAM for shared memory
    • Up to 6 masters, 4x 64-bit read, 4x 64-bit write data
  • Miscellaneous
    • FPGA-to-HPS interrupts
    • DMA handshake (allows FPGA peripherals to perform block-level transfers with system DMA controller)
    • More than 100Gbps HPS-to-FPGA and FPGA-to-HPS bandwidth

Altera Cyclone® V SoC Family


Altera Cyclone® V 28nm SoCs provide the industry's lowest system cost and power, along with performance levels that make the device family ideal for differentiating high-volume applications. They offer up to 40% lower total power compared with the previous generation, efficient logic integration capabilities, integrated transceiver variants, and SoC variants with an ARM-based hard processor system (HPS).
Learn more


Features
  • Integrated HPS lets the user reduce system power, system cost, and board space:
    • Consists of processors, peripherals, and memory controller
  • Performance and ecosystem of an applications-class ARM® processor combined with the flexibility, low cost, and low power consumption of the Cyclone V FPGAs

Dual-Core ARM Cortex-A9 MPCore Processor Features
  • 800MHz dual-core processor supporting symmetric and asymmetric multiprocessing
  • Each processor includes the following:
    • High-efficiency, dual-issue superscalar pipeline (2.5MIPS/MHz)
    • NEON™ media processing engine for media and signal processing acceleration
    • Single- and double-precision floating-point unit
    • 32KB instruction and 32KB data caches
    • Cache coherence for enhanced inter-processor communication
    • Memory Management Unit with TrustZone® security technology
    • Thumb®-2 technology for enhanced code density, performance, and power efficiency
    • Jazelle® architecture extensions for accelerating Java Virtual Machine
    • Program Trace Macrocell for full visibility of processor instruction flow
  • Shared 512KB, 8-way associative L2 cache, lockable by way, line, or master
  • Acceleration coherency port that extends coherent memory access beyond the CPUs
  • Generic interrupt controller
  • 32-bit general purpose timer
  • Watchdog timer

Cyclone V SE SoC
Part Number LEs (K) Adaptive Logic Modules (ALMs) M10K Memory Blocks MLABs (Kb) 18-bit x 19-bit Multipliers Variable-Precision DSP Blocks FPGA PLLs HPS PLLs Max FPGA User I/Os Max HPS I/Os Processor Cores (ARM Cortex™-A9 MPCore™)
5CSEA2 25 9434 140 138 72 36 4 3 145 188 Single or Dual
5CSEA4 40 15094 224 220 116 58 5 3 145 188 Single or Dual
5CSEA5 85 32075 397 480 174 87 6 3 288 188 Single or Dual
5CSEA6 110 41509 514 621 224 112 6 3 288 188 Single or Dual

Cyclone V SX SoC
Part Number LEs (K) ALMs M10K Memory Blocks MLABs (Kb) 18-bit x 19-bit Multipliers Variable-Precision DSP Blocks Max XCVRs PCIe Hard IP Block FPGA PLLs HPS PLLs Max FPGA User I/Os Max HPS I/Os Processor Cores (ARM Cortex™-A9 MPCore™)
5CSXC2 25 9434 140 138 72 36 6 2 4 3 145 188 Dual
5CSXC4 40 15094 224 220 116 58 6 2 5 3 145 188 Dual
5CSXC5 85 32075 397 480 174 87 9 2 6 3 288 188 Dual
5CSXC6 110 41509 514 621 224 112 9 2 6 3 288 188 Dual

Cyclone V ST SoC
Part Number LEs (K) ALMs M10K Memory Blocks MLABs (Kb) 18-bit x 19-bit Multipliers Variable-Precision DSP Blocks Max XCVRs PCIe Hard IP Block FPGA PLLs HPS PLLs Max FPGA User I/Os Max HPS I/Os Processor Cores (ARM Cortex™-A9 MPCore™)
5CSTD5 85 32075 397 480 174 87 9 2 6 3 288 188 Dual
5CSTD6 110 41509 514 621 224 112 9 2 6 3 288 188 Dual

Reducing Total System Cost Through Integration


Because Cyclone V integrate an abundance of hard intellectual property (IP) blocks, the user can differentiate and do more with less overall system cost, power, and design time. Key hard IP blocks include the following:

  • Hard memory controllers supporting 400MHz DDR3 SDRAM with optional error correction code (ECC) support
  • PCI Express® (PCIe®) Gen2 with multifunction support
  • Variable-precision digital signal processing (DSP) blocks
  • HPS Dual-core ARM Cortex-A9 MPCore processor

Cyclone V System Level Cost Savings Through Integration

Cyclone V FPGA System Level Cost Savings Through Integration

Altera SoC Development Tools


Altera offers a range of software development tools, hardware development tools, and development kits that include everything needed to quickly and easily create and implement new designs.

Altera Cyclone V SoC Development Kit

Kit Includes
  • Board, power supply, cables, reference design
  • Comes with the full SoC Embedded Design Suite
  • Uses Quartus II Web Edition design software

Features
  • Integrated HPS lets the user reduce system power, system cost, and board space:
    • Consists of processors, peripherals, and memory controller
  • Performance and ecosystem of an applications-class ARM® processor combined with the flexibility, low cost, and low power consumption of the Cyclone V FPGAs

Altera Cyclone V SoC Development Board Block Diagram

Altera Cyclone V SoC Development Board Block Diagram

Altera SoC Virtual Target

Altera offers the SoC Virtual Target, a virtual prototyping platform to enable pre-silicon and post-silicon software development. The Altera SoC Virtual Target is a fast functional simulation of a dual-core ARM® Cortex™-A9 MPCore™ embedded processor development system. This complete prototyping tool, which models a real development board, runs on a PC and boots the Linux operating system out of the box. Designed to be binary- and register-compatible with the real hardware that it simulates, the Virtual Target enables the development of device-specific, production software that can run unmodified on real hardware.

Virtual prototyping tools are preferred for software development because of their added level of full-system visibility and control. Using a virtual prototyping tool, the user can jump start software development well in advance of hardware availability, make their software team more productive, and improve software quality.

To fully represent Altera's SoC devices, the Virtual Target also features an FPGA extension to the PC-based simulation called FPGA-in-the-loop. FPGA-in-the-loop allows the Virtual Target to interface to an Altera off-the-shelf FPGA development board, where the user can implement custom intellectual property (IP) and co-execute it with the other components of the Virtual Target that runs on the PC. This allows testing of software with FPGA hardware such as custom peripherals and hardware accelerators.


Virtual Target with Optional FPGA-in-the-Loop
Virtual Target with Optional FPGA-in-the-Loop

Features & Benefits
  • Proven technology - Virtual prototyping tools are industry-proven solutions that enable pre-silicon software development and shorten time to market. Many successful semiconductor companies, including Altera, are using virtual prototyping tools based on the Synopsys Innovator Platform.
  • Ready to use - The Virtual Target is a pre-built, fully functional simulation model of a complete embedded system that runs out of the box. You need no prior modeling or simulation experience. The Virtual Target works with your existing software tools, such as GDB, TRACE32 from Lauterbach and DS-5 from ARM, and Wind River Workbench.
  • Device specific - The code written for the Virtual Target is binary- and register-compatible with the modeled board and can run on both platforms without modification.
  • Linux enabled - The Virtual Target comes with a Linux boot image and drivers to support all the major components of the system.
  • Fast simulation speed - The Virtual Target is a fast functional simulation that can boot Linux in 20 seconds.
  • Full system visibility and control - The Virtual Target allows you to perform tasks that are difficult or impossible on real hardware.
Jump-Start Software Development with the SoC Virtual Target


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