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Home » NEWEST Products » New by Manufacturer » Altera Corporation » Altera Max II / MAX IIG / MAX IIZ CPLDs
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Altera MAX® II / IIG / IIZ CPLDs

Altera MAX® II / IIG / IIZ CPLDs

Altera MAX® II / IIG / IIZ CPLDs

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Altera MAX® II CPLD family devices are the lowest power, lowest cost CPLDs ever. Altera MAX II CPLD family is based on a groundbreaking architecture that delivers the lowest power and the lowest cost per I/O pin of any CPLD family. With the introduction of the MAX IIZ CPLD, there are now three variants that all use the same innovative CPLD architecture: MAX II, MAX IIG, and MAX IIZ. Zero-power MAX IIZ CPLDs offer the same non-volatile, instant-on advantages found in the low-cost MAX II CPLD family and are applicable to a wide range of functions and applications. MAXII is an instant-on, non-volatile CPLD family that targets general-purpose, low-density logic and portable applications, such as cellular handset design.


Features
  • Low-cost, low-power CPLD
  • Instant-on, non-volatile architecture
  • Standby current as low as 25 μA
  • Provides fast propagation delay and clock-to-output times
  • Provides four global clocks with two clocks available per logic array block (LAB)
  • UFM block up to 8 Kbits for non-volatile storage
  • MultiVolt core enabling external supply voltages to the device of either 3.3 V/2.5 V or 1.8 V
  • MultiVolt I/O interface supporting 3.3-V, 2.5-V, 1.8-V, and 1.5-V logic levels
  • Bus-friendly architecture including programmable slew rate, drive strength, bus-hold, and programmable pull-up resistors
  • Schmitt triggers enabling noise tolerant inputs (programmable per pin)
  • I/Os are fully compliant with the Peripheral Component Interconnect Special Interest Group (PCI SIG) PCI Local Bus Specification, Revision 2.2 for 3.3-V operation at 66 MHz
  • Supports hot-socketing
  • Built-in Joint Test Action Group (JTAG) boundary-scan test (BST) circuitry compliant with IEEE Std. 1149.1-1990
  • ISP circuitry compliant with IEEE Std. 1532
Applications
  • Power-up sequencing
  • System configuration
  • I/O expansion
  • Interface bridging

MAX II Features
Part Number LEs Typical Equivalent Macrocells Equivalent Macrocell Range UFM Size (bits) Max User I/O Pins
EPM240 240 192 128 to 240 8192 80
EPM240G 240 192 128 to 240 8192 80
EPM570 570 440 240 to 570 8192 160
EPM570G 570 440 240 to 570 8192 160
EPM1270 1270 980 570 to 1270 8192 212
EPM1270G 1270 980 570 to 1270 8192 212
EPM2210 2210 1700 1270 to 2210 8192 272
EPM2210G 2210 1700 1270 to 2210 8192 272
EPM240Z 240 192 128 to 240 8192 80
EPM570Z 570 440 240 to 570 8192 160

MAX II Block Diagram
MAX II Block Diagram

Altera's commitment to low-power, restricted space, extended temperature, and low-cost application development is on display with the improved zero-power MAX® IIZ CPLDs. Zero-power MAX IIZ CPLDs offer the same non-volatile, instant-on advantages found in the low-cost MAX II CPLD family and are applicable to a wide range of functions and applications


MAX IIZ Key Features
  • Zero standby power
  • Ultra-small, easy-to-use package
  • Instant-on, non-volatile advantage
  • Commercial (0 to 85°C) and industrial (-40 to 100°C) temperature ranges
  • In-system programmability (ISP)
  • Free Quartus® II and ModelSim®-Altera Web Edition software
  • Ideal for Portable Applications
    • Low power consumption—as low as 25 µA.
    • With the industry's lowest dynamic and static power consumption, MAX IIZ devices can meet the needs of the most demanding battery or low-power applications

MAX IIZ Application Areas
MAX IIZ Application Areas
Altera MAX® II Development Kit

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Altera MAX® II Development Kit

Altera DK-MAXII-1270N MAX® II Development Kit, from the market's leading supplier of CPLDs, enables you to evaluate the MAX II CPLD feature set or begin prototyping your own design. This Altera dev kit includes reference designs (LCD controller, PCI, USB, and slot machine), demo designs, software, cables, and all the accessories needed to ensure fast and easy use of the MAX II CPLD.


Kit Contents
  • RoHS-compliant MAX II development board, PCI edge form factor
    • MAX II CPLD, EPM1270F256C5N
    • SRAM (128K x 8 bit)
    • 4-channel analog-to-digital converter (8-bit resolution)
    • USB media access control (MAC) with physical layer (PHY)
    • 16x2 character LCD module
    • Temperature gauge with serial peripheral interface (SPI)
    • Onboard power meter
    • Active I/O sense circuitry
    • Four user-defined, push-button switches
    • Four user-defined LEDs
  • Connectors
    • PCI edge form factor (3.3-V and 5.0-V tolerant)
    • JTAG connectors
    • USB connector (Type B)
    • One 3.3-V tolerant expansion/prototype header (41 available user I/O pins)
  • Cables and accessories
    • USB Blaster™ download programming cable
    • Type A-B USB cable (3 feet)
  • Reference designs and demos for MAX II CPLDs (partial list):
    • USB reference design (with software drivers)
    • PCI 32-bit target reference design (with software drivers)
    • LCD controller reference design
    • Low power demo
    • Real-time in-system programmability (ISP) demo
  • Quartus® II Web Edition design software
  • Complete documentation

Max II Development Board Top View
Max II Development Board Top View

MAX II Dev Board Block Diagram
MAX II Dev Board Block Diagram
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