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Home » NEWEST Products » New by Manufacturer » Altera Corporation » Altera MAX™ CPLD Series
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Altera MAX® CPLD Series
Altera MAX® CPLD Series

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Altera MAX® CPLD Series

Altera MAX® complex programmable logic device (CPLD) Series provides you with the lowest power, lowest cost CPLDs. MAX V CPLD family, the newest family in the CPLD series, delivers the market's best value. Featuring a unique, non-volatile architecture and one of the industry's largest density CPLDs, MAX V devices provide robust new features at lower total power compared to competitive CPLDs. MAX II CPLD family, based on the same groundbreaking architecture, delivers low power and low cost per I/O pin. MAX II CPLDs are instant-on, non-volatile devices that target general-purpose, low-density logic and portable applications, such as cellular handset design. Zero power MAX IIZ CPLDs offer the same non-volatile, instant-on advantages found in the MAX II CPLD family and are applicable to a wide range of functions. Manufactured on an advanced 0.30-µm CMOS process, the EEPROM-based MAX 3000A CPLD family provides instant-on capability and offers densities from 32 to 512 macrocells.

MAX CPLD Series Introduction
Product Family Year of Introduction Process Technology Key Features
MAX V 2010 0.18 µm Low Cost and Power
MAX IIZ 2007 0.18 µm Zero Power
MAX II 2004 0.18 µm I/O Count
MAX 3000A 2002 0.30 µm Low Cost
MAX 7000S 1995 0.5 µm 5.0-V I/Os

Altera MAX® V CPLDs

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Altera MAX® V CPLDs deliver the industry's best value in low cost, low power CPLDs, offering robust new features at up to 50% lower total power when compared to competitive CPLDs. Altera's MAX V also features a unique, non-volatile architecture and one of the industry's largest density CPLDs. In addition, the MAX V integrates many functions that were previously external, such as flash, RAM, oscillators, and phase-locked loops, and in many cases, it delivers more I/Os and logic per footprint at the same price as competitive CPLDs. The MAX V utilizes green packaging technology, with packages as small as 20mm2. MAX V CPLDs are supported by Quartus II® Software v.10.1, which allows productivity enhancements resulting in faster simulation, faster board bring-up, and faster timing closure.


Features
  • Extended battery life with static power as low as 45uW
  • As few as one power supply (Vcc-core) required, which also lowers bill of materials (BOM) costs
  • Digital PLLs (DPLLs), which enable flexible implementation of designs requiring frequency multiplication or phase shifting
  • In-system programming (ISP), which lets you program the device while it is in operation, so you can perform in-field updates without affecting overall system operation
  • User flash memory, embedded flash memory that provides non-volatile memory storage of critical system information
Applications
  • Wireline and Wireless
    • I/O expansion
  • Industrial and Military
    • Interface bridging (i.e. between different voltage and I/O standards)
  • Consumer
    • Power management control, sequencing, or monitoring
  • Broadcast
    • Initialization control (i.e. of DSPs, processors)

Block Diagram
Block Diagram
Altera MAX® II / IIG / IIZ CPLDs

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Altera MAX® II CPLD family devices are the lowest power, lowest cost CPLDs ever. Altera MAX II CPLD family is based on a groundbreaking architecture that delivers the lowest power and the lowest cost per I/O pin of any CPLD family. With the introduction of the MAX IIZ CPLD, there are now three variants that all use the same innovative CPLD architecture: MAX II, MAX IIG, and MAX IIZ. Zero-power MAX IIZ CPLDs offer the same non-volatile, instant-on advantages found in the low-cost MAX II CPLD family and are applicable to a wide range of functions and applications. MAXII is an instant-on, non-volatile CPLD family that targets general-purpose, low-density logic and portable applications, such as cellular handset design.


Features
  • Low-cost, low-power CPLD
  • Instant-on, non-volatile architecture
  • Standby current as low as 25 μA
  • Provides fast propagation delay and clock-to-output times
  • Provides four global clocks with two clocks available per logic array block (LAB)
  • UFM block up to 8 Kbits for non-volatile storage
  • MultiVolt core enabling external supply voltages to the device of either 3.3 V/2.5 V or 1.8 V
  • MultiVolt I/O interface supporting 3.3-V, 2.5-V, 1.8-V, and 1.5-V logic levels
  • Bus-friendly architecture including programmable slew rate, drive strength, bus-hold, and programmable pull-up resistors
  • Schmitt triggers enabling noise tolerant inputs (programmable per pin)
  • I/Os are fully compliant with the Peripheral Component Interconnect Special Interest Group (PCI SIG) PCI Local Bus Specification, Revision 2.2 for 3.3-V operation at 66 MHz
  • Supports hot-socketing
  • Built-in Joint Test Action Group (JTAG) boundary-scan test (BST) circuitry compliant with IEEE Std. 1149.1-1990
  • ISP circuitry compliant with IEEE Std. 1532
Applications
  • Power-up sequencing
  • System configuration
  • I/O expansion
  • Interface bridging

MAX II Block Diagram
MAX II Block Diagram
Altera MAX 3000A CPLDs

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Altera MAX 3000A 3.3-V CPLDs are cost-optimized, EEPROM-based family that provides instant-on capability and offers densities from 32 to 512 macrocells. MAX 3000A CPLDs support in-system programmability (ISP) and can be easily reconfigured in the field. Each MAX 3000A macrocell is individually configurable for either sequential or combinatorial logic operation. Altera's MAX 3000A programmable logic devices are the ideal non-volatile, instant-on CPLDs for high-volume, cost-sensitive applications.


Features
  • High–performance, low–cost CMOS EEPROM–based programmable logic devices (PLDs) built on a MAX® architecture
  • 3.3-V in-system programmability (ISP) through the built–in IEEE Std. 1149.1 Joint Test Action Group (JTAG) interface with advanced pin-locking capability
    • ISP circuitry compliant with IEEE Std. 1532
  • Built–in boundary-scan test (BST) circuitry compliant with IEEE Std. 1149.1-1990
  • Enhanced ISP features:
    • Enhanced ISP algorithm for faster programming
    • ISP_Done bit to ensure complete programming
    • Pull-up resistor on I/O pins during in–system programming
  • High–density PLDs ranging from 600 to 10,000 usable gates
  • 4.5–ns pin–to–pin logic delays with counter frequencies of up to 227.3 MHz
  • MultiVolt™ I/O interface enabling the device core to run at 3.3 V, while I/O pins are compatible with 5.0–V, 3.3–V, and 2.5–V logic levels
  • Pin counts ranging from 44 to 256 in a variety of thin quad flat pack (TQFP), plastic quad flat pack (PQFP), plastic J–lead chip carrier (PLCC), and FineLine BGAT™ packages
  • Hot–socketing support
  • Programmable interconnect array (PIA) continuous routing structure for fast, predictable performance
  • Industrial temperature range
Applications
  • Communication
  • Computer
  • Consumer
  • Automotive
  • Industrial
Altera MAX® V Development Kit

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Altera MAX® V Development Kit

Altera DK-DEV-5M570ZN MAX V CPLD Development Kit, from the market's leading supplier of CPLDs, provides a comprehensive, low-cost hardware platform to quickly begin developing low-cost, low-power CPLD designs. The development board was designed to prototype the most common CPLD applications, including I/O expansion, interface bridging, power management control, configuration and initialization control, and analog interface control.


With this platform, you can:
  • Develop designs for the 5M570Z CPLD
  • Measure CPLD power (VCCINT and VCCIO)
  • Bridge between two different I/O voltages (adjustable VCCIO on CPLD Bank 2)
  • Interface to external functions or devices via four connectors
  • Read and write to memories:
    • 8-Kbit (Kb) user flash memory (UFM) available within 5M570Z CPLD
    • I²C or SPI EEPROMs (user installed)
  • Come up to speed quickly with your CPLD design by reusing the example designs provided
  • Re-use the kit's PCB board and schematic as a model for your design


Altera MAX® II Development Kit

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Altera MAX® II Development Kit

Altera DK-MAXII-1270N MAX® II Development Kit, from the market's leading supplier of CPLDs, enables you to evaluate the MAX II CPLD feature set or begin prototyping your own design. This Altera dev kit includes reference designs (LCD controller, PCI, USB, and slot machine), demo designs, software, cables, and all the accessories needed to ensure fast and easy use of the MAX II CPLD.


Kit Contents
  • RoHS-compliant MAX II development board, PCI edge form factor
    • MAX II CPLD, EPM1270F256C5N
    • SRAM (128K x 8 bit)
    • 4-channel analog-to-digital converter (8-bit resolution)
    • USB media access control (MAC) with physical layer (PHY)
    • 16x2 character LCD module
    • Temperature gauge with serial peripheral interface (SPI)
    • Onboard power meter
    • Active I/O sense circuitry
    • Four user-defined, push-button switches
    • Four user-defined LEDs
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  • Altera Corporation
  • Semiconductors|Embedded Processors|IC-Programmable Logic