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Home » NEWEST Products » New by Manufacturer » Altera Corporation » Arria V Midrange FPGAs - Altera
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Altera Arria V Midrange FPGAs

Altera Arria® V Midrange FPGAs

Altera Arria® V Midrange FPGAs consists of the most comprehensive offerings of mid-range FPGAs ranging from the lowest power for 6-gigabits per second (Gbps) and 10-Gbps applications, to the highest mid-range FPGA bandwidth 12.5Gbps transceivers. The Arria® V devices are ideal for power-sensitive wireless infrastructure equipment, 20G/40G bridging, switching, and packet processing applications, high-definition video processing and image manipulation, and intensive digital signal processing (DSP) applications.

Additional Resources:
Arria V Device Handbook Arria® V Device Handbook
Arria V Device Datasheet Arria® V Device Datasheet
Arria V Device Overview Arria® V Device Overview
Arria V PowerPlay Early Power Estimator User Guide Arria® V PowerPlay Early Power Estimator User Guide
Arria V PowerPlay Power Estimator Arria® V PowerPlay Early Power Estimator
Altera Arria Video Webinar
  • Two Variants:
      • Arria V GT FPGAs offer the lowest power mid-range FPGA for applications that require up to 20 transceivers at 10.3125 Gbps and SFF 8431 compliance
      • Arria V GX FPGAs offer the lowest power midrange FPGA for applications that require up to 32 backplane-capable 6.5536 Gbps transceivers
  • Lowest static power in its class
  • Improved logic integration and differentiation capabilities
  • Increased bandwidth capacity
  • Hard processor system (HPS) with integrated ARM® Cortex™-A9 MPCore processor
  • Lowest system cost
  • TSMC's 28nm process technology
  • Thermal composite flip chip BGA packaging
  • High-performance FPGA fabric
  • Internal memory blocks
      • M10K—10-kilobits (Kb) memory blocks with soft error correction code (ECC)
      • M20K—20-Kb memory blocks with hard ECC (Arria V GZ devices only)

  • Memory logic array block (MLAB)—640-bit distributed LUTRAM where you can use up to 50% of the ALMs as MLAB memory
  • Embedded Hard IP blocks
  • Clock networks
    • Up to 650 MHz global clock network
    • Global, quadrant, and peripheral clock networks
    • Clock networks that are not used can be powered down to reduce dynamic power
  • Phase-locked loops (PLLs)
  • FPGA General-purpose I/Os (GPIOs)
  • External Memory Interface
  • Memory interfaces with low latency:
  • Low-power high-speed serial interface

  • Lowest total power for mid-range applications in:
  • Remote Radio Units
  • 10G / 40G Line Cards
  • Broadcast Studio Equipment

Arria® V
Arria® V
Arria® V Architecture
ALMs (K) 170 190
Variable-Precision DSP 1,139 1,156
M20K Blocks 1700 -
M10K Blocks - 2414
DDR3 Memory Interface Speed 800 MHz 667 MHz
Hard Memory Controllers - 4
Transceivers (Gbps) 12.5 Gbps 10.3125
PCI Express (PCIe) 1 -
Gen3/2/1 HIP 1 -
PICe Gen2/1 HIP - 2
Design Security Yes Yes
SEU Mitigation Yes Yes

Altera® Arria® V GX FPGA Development Kit

The Altera® Arria® V GX FPGA Development Kit provides a complete design environment that includes all the hardware and software that you need to develop full FPGA designs and test them within a system environment. The development kit is RoHS compliant, and includes features of two FPGAs for system-level design, three I/O expansion slots, 2 GB of DDR3 SDRAM memory, 4.5 MB of QDR II+ memory, and 1 Gb of flash memory, SFP+ connections, SMAs and the new Samtec Bullseye and the ability to measure individual power rails on each chip.

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