The bus terminals of the SN65HVD7x transceiver family possess on-chip ESD protection against ±15 kV human body model (HBM) and ±12 kV IEC61000-4-2 contact discharge. The IEC-ESD test is far more severe than the HBM-ESD test. The 50 % higher charge capacitance, CS, and 78 % lower discharge resistance, RD of the IECmodel produce significantly higher discharge currents than the HBM-model.
While the implementation of IEC-ESD protection on-chip increases the robustness of portable equipment significantly, it is certainly insufficient to protect a transceiver against the high-energy battering from electrical fast transients (EFT) pulse trains and surge transients, no matter how small the transient voltage and surge transients. In the case of a sequence of electrical fast transients, also known as pulse train, the constant bombardment of these transients does not allow the internal protection circuits to recover. The electrical energy of a transient that is dumped onto the transceiver’s internal protections cells is converted into thermal energy, or heat that literally fries the protection cells, thus destroying the transceiver.
It is obvious that even a 15 kV IEC-ESD protection circuit will barely survive a single, 1 kV EFT pulse, let alone a 4 kV EFT pulse-train, which has risen to the standard requirement in many industrial automation and e-metering applications. In order to protect bus nodes against high-energy transients, the implementation of external transient protection devices is therefore necessary. The figure below suggests a design providing protection against light and heavy surge transients, in addition to ESD and EFT transients. It provides surge protection of ≥ 500 V transients only, while the right protection circuits can withstand surge transients of 5 kV.