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Home » NEWEST Products » New by Manufacturer » Texas Instruments » LMK00334/38 Clock Buffer/Level Translator - Texas Instruments
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Texas Instruments LMK00334/38 Clock Buffer/Level Translator

Texas Instruments LMK00334/38 Clock Buffer/Level Translator

Texas Instruments LMK00334/38 Clock Buffer/Level Translator is intended for high-frequency, low-jitter clock/data distribution and level translation. The input clock can be selected from two universal inputs or one crystal input. The selected input clock is distributed to two banks of 2 HCSL (4 HCSL LMK00338) outputs and one LVCMOS output. The LVCMOS output has a synchronous enable input for runt-pulse-free operation when enabled or disabled. The LMK00334/38 operates from a 3.3 V core supply and 3 independent 3.3 V/2.5 V output supplies. The LMK00334/38 provides high performance, versatility, and power efficiency, making it ideal for replacing fixed-output buffer devices while increasing timing margin in the system.

Features
  • 3:1 Input Multiplexer
    • Two Universal Inputs Operate up to 400 MHz and Accept LVPECL, LVDS, CML, SSTL, HSTL, HCSL, or Single-Ended Clocks
    • One Crystal Input Accepts a 10 to 40 MHz Crystal or Single-Ended Clock
  • Two Banks with 2 Differential Outputs Each
    • HCSL, or Hi-Z (Selectable)
    • Additive RMS Phase Jitter for PCIe Gen3 at 100MHz: 30 fs RMS (typical)
  • High PSRR: -72 dBc at 156.25 MHz
  • LVCMOS Output with Synchronous Enable Input
  • Pin-Controlled Configuration
  • VCC Core Supply: 3.3 V ± 5%
  • 3 Independent VCCO Output Supplies: 3.3 V/2.5 V ± 5%
  • Industrial Temperature Range: -40°C to +85°C
  • 32-lead WQFN - 5 mm x 5 mm (LMK00334)
  • 40-lead WQFN - 6 mm x 6 mm (LMK00338)
Applications
  • Clock Distribution and Level Translation for ADCs, DACs, Multi-Gigabit Ethernet, XAUI, Fibre Channel, SATA/SAS, SONET/SDH, CPRI, High-Frequency Backplanes
  • Switches, Routers, Line Cards, Timing Cards
  • Servers, Computing, PCI Express (PCIe 3.0)
  • Remote Radio Units and Baseband Unit

Functional Block Diagram
Functional Block Diagram

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