NXP LPC800 ARM Cortex™-M0+ 32-bit microcontrollers (MCUs) are available in low pin-count packages and offer easy-to-use peripherals addressing 8-bit application requirements while providing the 32-bit capabilities and exceptional power efficiency of the ARM® Cortex-M0 processor. Based on an ultra-low-power 30-MHz ARM Cortex-M0+ processor, LPC800 is fully compatible with the Cortex-M architecture and instruction set and offers superior code density to 8- / 16-bit architectures. The Cortex-M0+ features a two-stage pipeline that reduces power consumption while improving performance. LPC800 MCUs also take advantage of the Cortex-M0+ peripheral bus, allowing single-cycle access to the GPIOs. These features enable NXP LPC800 devices to offer deterministic, real-time performance - a key requirement for 8-bit developers.
LPC800 includes game-changing features, such as a switch matrix that enables designers to assign on-chip peripherals to any pin with a single line of code or a single click in the configuration tool. LPC800 serial peripherals are designed to be as lean as possible, making them more responsive and efficient. The new SPI can operate as a slave at frequencies independent of the processor clock, solving the common frustration of having to over-sample 4-to-n times the SPI just to receive data. This decoupling of the SPI and processor clock speed reduces power and simplifies the system design. The I²C has also been re-engineered to allow the LPC800 to lie and wait at near-zero power consumption, even without a system clock, and wake up upon an address match.
New! Embedded Artists LPC812 MAX Experiment Kit has been created as a guided tour to learn embedded programming with the mbed framework and the NXP's LPC800 microcontroller family with Cortex-M0+ cores. The experiments are performed on a breadboard for maximum flexibility and ease of use.
NXP LPC810 / LPC811 / LPC812 Features
Boot ROM API support:
- 16 kB on-chip flash programming memory.
- 4 kB SRAM.
- In-System Programming (ISP) and In-Application Programming (IAP) via on-chip boot loader software.
- UART drivers
- I²C drivers
- Power profiles
- High-speed GPIO interface connected to the ARM Cortex-M0+ IO bus with up to 18 General Purpose I/O (GPIO) pins with configurable pull-up/pull-down resistors.
- Pin interrupt generation capability with boolean pattern-matching feature on up to Eight selectable GPIO inputs.
- Switch matrix for flexible configuration of each I/O pin function.
- State Configurable Timer (SCT) with input and output functions (including capture and match) assigned to pins through the switch matrix.
- Multiple-channel multi-rate timer for repetitive interrupt generation at up to four programmable, fixed rates.
- Wake-up timer for self-timed wake-up from reduced power modes.
- CRC engine.
- Windowed Watchdog timer
- Comparator with external voltage reference with pin functions assigned through the switch matrix.
- Internal reference voltage.
- Three UART interfaces with pin functions assigned through the switch matrix.
- Two SPI controllers with pin functions assigned through the switch matrix.
- - One I²C-bus interface with open-drain full I²C spec fast Modeplus.
- 12 MHz internal RC oscillator trimmed to 1% accuracy that can optionally be used as a system clock.
- Crystal oscillator with an operating range of 1 MHz to 25 MHz.
- Programmable watchdog oscillator with a frequency range of 9.4 kHz to 2.3 MHz.
- PLL allows CPU operation up to the maximum CPU rate without the need for a high-frequency crystal. May be run from the external clock input (CLKIN), the system oscillator, or the internal RC oscillator.
- Integrated PMU (Power Management Unit) to minimize power consumption.
- Reduced power modes (Sleep, deep-sleep, power-down, deep power-down).
- Power-On Reset (POR).
- Brownout detect.
- Available as SO20 package, TSSOP20 package, TSSOP16, and DIP8 package.