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Home » NEWEST Products » New by Manufacturer » Cypress Semiconductor » CYFB0072V Video Frame Buffer - Cypress
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Cypress CYFB0072V Video Frame Buffer

Cypress CYFB0072V Video Frame Buffer

Cypress CYFB0072V Video Frame Buffer is a 72-Mbit First-In, First-Out (FIFO) memory device designed to meet the market’s increasing demand for high-bandwidth video buffering. CYFB0072V provides independent read and write ports, which can be clocked up to 133 MHz. The device's bus size of 36 bits enables a data throughput of 4.8 Gbps. In addition, CYFB0072V offers a simple and easy-to-use interface to reduce implementation and debugging efforts, improve time-to-market, and reduce engineering costs. The Cypress CYFB0072V Video Frame Buffer is an ideal memory choice for a wide range of applications including video and image processing or any system that needs buffering at high speeds across different clock domains.

  • Memory organization
    • Density: 72-Mbit
    • Organization: × 36
  • Up to 133-MHz clock operation[1]
  • Unidirectional operation
  • Independent read and write ports
    • Supports simultaneous read and write operations
    • Reads and writes operate on independent clocks, up to a maximum ratio of two, enabling data buffering across clock domains.
    • Supports multiple I/O voltage standard: low voltage complementary metal oxide semiconductor (LVCMOS) 3.3 V and 1.8 V voltage standards.
  • Input and output enable control for write mask and read skip operations
  • Empty & Full status flags
  • Flow-through mailbox register to send data from input to output port, bypassing the Frame Buffer
  • Separate serial clock (SCLK) input for serial programming of configuration registers
  • Master reset to clear entire Frame Buffer
  • Partial reset to clear data but retain programmable settings
  • Joint test action group (JTAG) port provided for boundary scan function
  • Industrial temperature range: –40°C to +85°C
1. For device operating at 150 MHz, Contact Sales.

 Logic Block Diagram
Cypress CYFB0072V Video Frame Buffer Logic Block Diagram
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