Analog Devices DPG3 Pattern Generator
Analog Devices DPG3, or Data Pattern Generator 3, is a device designed to support the evaluation of Analog Devices' High-Speed Digital-to-Analog Converters (DAC). The device is connected to a PC over USB, and allows a user to download a data vector into the DPG3, which is then played out to an attached DAC evaluation board at full speed.
- Converter Interfaces
- CMOS Interface
- 32-bits (shared with the P lines of the LVDS bus)
- Up to 250Mbps per bit (SDR)
- Same connector and pinout as DPG2
- LVDS Interface
- 32-bits (P lines shared with CMOS interface)
- Up to 1.6Gbps per bit (800MHz DDR)
- Same connector and pinout as DPG2
- High-Speed Serial Interface (For JESD204 Converters)
- 16 Tx lanes
- Up to 8.5Gbps per lane
- Dual DDR3 SO-DIMM
- Maximum pattern length of 134M samples (limited to 30M samples in most 3rd party software)
- PC Interface
- On-connector clock input for all interfaces
- Optional external clock input via front-panel SMA jack for CMOS and LVDS interfaces
- SMA jack for trigger input or output
- Multi-Unit Synchronization
- Up to four DPG3's may have their LVDS interfaces synchronized together
- Requires additional Synchronization Board and cabling
- Specified for operation at 25ºC only
The clocking system varies between the traditional CMOS/LVDS interfaces and the newer high-speed serial interface. In all cases, the DPG needs to be provided with a clock. It cannot generate a data clock internally.
Most evaluation boards will supply a clock to the DPG over the CMOS/LVDS connector. In all cases, this clock is LVDS, even if the rest of the interface is CMOS. A clock will be provided with the data that is synchronous to the data (source synchronous), which will match the format of the data.
Alternatively, a clock can be provided externally via the SMA jack on the front of the unit. In this case, the clock's amplitude must be +4dBm. This method is not recommended for general use. To enable the external clock operation, click the Advanced/Debug button in DPGDownloader, and select Front panel SMA jack as the Clock Source in the Clock section.
The high-speed serial transceivers inside the DPG3 require a reference clock in order to be able to lock on to the embedded clock inside the serial data stream. This clock must be provided over the connector to the evaluation board.
The SMA jack on the front of the unit for the trigger can be used either as an input or as an output trigger. To enable the trigger, click Advanced/Debug in DPGDownloader, and check the Enable Trigger box in the Trigger section.
The input high threshold is 2.0V, and the input low threshold is 0.8V, allowing it to be directly interfaced with 3.3V logic signals.
When set as an output, the trigger will pulse when the playback is running at the beginning of the vector. Therefore, it will pulse every time the vector is looped when in Loop mode, or only once if the unit is in Count mode.
With the appropriate external synchronization board and cables, up to four DPG3's can be synchronized together when in LVDS mode. One unit is designated as the master, and all units use the master's clock instead of their own. The data will then being playback from each unit on the same clock edge.
Synchronizing multiple DPGs together does not guarantee that the analog waveforms coming out of the attached DAC evaluation board are synchronized. Each particular DAC may require additional synchronization circuitry to ensure that the analog outputs are synchronized.
Note that the synchronization board and cables used with the DPG2 are not compatible with the DPG3.
Multi-Unit Synchronization is not currently supported on the DPG3, but will be enabled by a future software update.
The DGP3 has two separate connector systems for interfacing with evaluation boards. One, for CMOS and LVDS interface DACs, is backwards compatible with the DPG2. The second connector is new to the DPG3, and supports high-speed serial, power, and communications.
The CMOS/LVDS connection on DPG2 and DPG3 uses two AMP/Tyco 1469169-1 connectors, placed side-by-side, with 139.2mil spacing between the centers of the innermost pins on both connectors. The mating connector on the evaluation board side is two AMP/Tyco 1469028-1. Note that both connectors are always required.
Left Side Connector
The left connector when looking at the connection on the DPG from the evaluation board side (J17 on the DPG2, J8 on the DPG3).
Right Side Connector
The right connector when looking at the connection on the DPG from the evaluation board side (J18 on the DPG2, J10 on the DPG3)
High-Speed Serial Connector
The second connector system on the DPG3 uses an FCi AirMax connector, part number 10057041-101LF. The mating connector used on the evaluation board is part number 10037324-101LF.
* The RX SERDES lines are not enabled, and can not be used with JESD204 ADCs.
† The SPI lines are not enabled. Communication with parts on the evaluation board is performed over the I2C link, and converted into SPI on the evaluation board.
The firmware of the DPG3 can be updated when new features or fixes are available. To update the firmware, click the Advanced/Debug button in DPGDownloader. Click the Update button in the Firmware section, and select the new firmware file. Do not interrupt the firmware update process. The unit may become inoperable if the update process is interrupted.
Legacy CMOS Boards
Some legacy evaluation boards for DACs with a CMOS data interface use a ribbon cable to connect to a pattern generator, instead of connecting directly. To use these boards on a DPG3, an adapter board is required. Please contact DPG Support to request this adapter board.
Please contact DPG Support with any additional questions regarding the DPG or DAC Software Suite.