Contact Mouser (USA)  (800) 346-6873     |     Feedback        
View Cart     |     Change Location  USD
United States United States

Please confirm your currency selection:

US Dollars
Home » NEWEST Products » New by Manufacturer » Analog Devices Inc. » ADN2917 Continuous Rate Clock & Data Recovery IC - Analog Devices
NEWEST Products
Analog Devices ADN2917 Continuous Rate Clock & Data Recovery IC

Analog Devices ADN2917 Continuous Rate
Clock & Data Recovery IC

Analog Devices ADN2917 Continuous Rate Clock & Data Recovery IC is designed to provide the receiver functions of quantization, signal level detect, and clock and data recovery for continuous data rates from 8.5-11.3Gbps. ADN2917 automatically locks to all data rates without requiring an external reference clock or programming. ADN2917 jitter performance exceeds all jitter specifications required by SONET/SDH, including jitter transfer, jitter generation, and jitter tolerance. The design also provides manual or automatic slice adjust and manual sample phase adjusts. Additionally, the designer can select a limiting amplifier or equalizer at the input. The equalizer is either adaptive or can be manually set. The receiver front-end loss of signal (LOS) detector circuit indicates when the input signal level has fallen below a user-programmable threshold. The LOS detect circuit has hysteresis to prevent chatter at the LOS output. In addition, the input signal strength can be read through the I²C registers.  ADN2917 also supports pseudorandom binary sequence (PRBS) generation, bit error detection, and input data rate readback features. The ADN2917 is available in a compact 4mm ×  4mm, 24-lead frame chip scale package (LFCSP). All ADN2917 specifications are defined over the ambient temperature range of −40°C to +85°C. Applications include SONET/SDH OC-192, 10GFC, 10GE & all associated FECs, XFP, line cards, clocks, routers, repeaters, instruments, and any rate regenerators/repeaters.

Features
  • Serial data input: 8.5Gbps to 11.3Gbps
  • No reference clock required
  • Exceeds SONET/SDH requirements for jitter transfer/generation/tolerance
  • Quantizer sensitivity:9.2 mVp-p typical (limiting amplifier mode)
  • Optional limiting amplifier and equalizer inputs
  • Programmable jitter transfer bandwidth to support G.8251 OTN
  • Programmable slice level
  • Sample phase adjust
  • Output polarity invert
  • Programmable LOS threshold via I²C
  • I²C to access optional features
  • LOS alarm(limiting amplifier mode only)
  • LOL indicator
  • PRBS generator/detector
  • Application-aware power
  • 352mW at 8.5Gbps, equalizer mode, no clock output
  • 430mW at 11.3Gbps, equalizer mode, no clock output
  • Power supplies: 1.2V, flexible 1.8V to 3.3V, and 3.3V
  • 4mm × 4mm 24-lead LFCSP
Applications
  • SONET/SDH OC-192, 10GFC, and 10GE and all associated FECs
  • XFP, line cards, clocks, routers, repeaters, instruments
  • Any rate regenerators/repeaters
Functional Block Diagram
Functional Block Diagram
eNews
  • Analog Devices Inc.