Lattice Semiconductor
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Lattice Semiconductor Corporation is a leading provider of Programmable Logic Devices, software, Intellectual Property, and development kits. The Mid-Range Lattice ECP3 family is the lowest power SerDes enabled FPGA available in the market. The MachXO is the most versatile non-volatile PLD targeted for low density applications such as platform management. Lattice also provides programmable Mixed Signal Power Management devices with unparalleled flexibility and integration. Lattice continues to deliver "More of the Best"
to its customers with comprehensive solutions for system design, including an
unequaled portfolio of high-performance, non-volatile, and low-cost FPGAs.
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Lattice Semiconductor Part Search
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Resources
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Lattice Semiconductor Platform Manager™ Development Kit
The Lattice Semiconductor Platform Manager™ Development Kit contains an evaluation board complete with evaluation code and documentation. Platform Manager ICs feature programmable analog with a CPLD and FPGA blocks all on one chip to integrate power and digital board management functions. The Lattice Platform Manager Development Kit allows users to see known good hardware in five minutes and recompile the provided source code to get to a known good starting point in only 30 minutes. This Lattice Semiconductor kit includes support circuits such as LEDs, an LCD display, DIP switches, and analog slider switches to aid in testing the Platform Manager's input/output capabilities. Also included is reserved space specifically for user-circuit prototyping.
Lattice Semiconductor Platform Manager™ Mixed-Signal ICs
Lattice Semiconductor Platform Manager™ mixed-signal ICs are a single-chip solution that integrates power management and digital board management functions, reducing design costs, enhancing system reliability, and providing a high degree of flexibility. Lattice Platform Manager mixed-signal devices monitor up to 12 voltage rails and support 47 (LPTM10-1247) or 107 digital I/Os (LPTM10-12107). The power management section consists of a programmable threshold, precision differential input comparator block with an accuracy of 0.7%, a 48-macrocell CPLD, programmable hardware timers, a 10-bit ADC, and a trim block for the trimming and margining of supplies. The digital board management section consists of a 640-LUT FPGA and programmable log interface I/O. Lattice Semiconductor Platform Manager devices are ideal for use in a broad range of applications with complex board management functions. Typical applications include wireless infrastructure, networking core equipment, server, data storage, and high-end industrial instrumentation.
Lattice ispPAC-POWR1220AT8 Power Manager
The ispPAC®-POWR1220AT8 Power Manager is a general-purpose power supply monitor, sequence and margin controller that incorporates both in-system programmable logic and analog functions implemented in non-volatile E²CMOS® technology. The ispPAC®-POWR1220AT8 offers many features and benefits, including ability to simultaneously monitor up to 12 power supplies and provide up to 20 output control signals, trim and margin for up to eight power supplies, dynamic voltage control through I²C, embedded PLD for sequence control, four embedded independent programmable timers, 12 independent analog monitor inputs, differential inputs for remote ground sense, high-voltage FET drivers, power supply ramp up/down control, 2-wire (I²C/SMBus™Compatible) interface , 3.3V operation, and wide supply range of 2.8V to 3.96V.
LatticeXP2 Brevia Development Kits & Reference Designs
Lattice Semiconductor Corp. now offers the easy-to-use, low cost, and versatile LatticeXP2™ Brevia Development Kit and 28 new silicon-proven reference designs ideal for developing high volume, cost sensitive, and high density applications. Designed for use with the popular LatticeXP2 FPGA line, Lattice's LatticeXP2™ Brevia Development Kits include the LatticeXP2 LFXP2-5E-6TN144C device, 2Mb SPI Flash and 1Mb SRAM memory, expansion headers, and several LEDs and user switches. The LatticeXP2 Development Kit's preloaded system-on-chip design allows designers to test within minutes UART interfaces, the 8-bit LatticeMico8™ soft microcontroller, and peripheral controllers for SPI and SRAM, and they can build their own designs using the free downloadable reference design codes, with many features implemented within an hour. The compact Brevia Development Kits can also be used for implementing elaborate micro-controller applications using the downloadable LatticeMico32™ soft processor.
Lattice LatticeECP3™ FPGAs
The LatticeECP3™ third generation high value FPGA from Lattice Semiconductor offers the industry's lowest consumption and price of any SERDES-capable FPGA device. The LatticeECP3 FPGA family offers multiprotocol 3.2G SERDES with XAUI jitter compliance, DDR3 memory interfaces, powerful DSP capabilities, high density on-chip memory, and up to 149K LUTS - all with half the power consumption and half the price of competitive SERDES-capable FPGAs. These Lattice FPGAs also provide flexible, reliable, and secure configuration options such as dual-boot capability, bit-stream encryption, and TransFR field upgrade features. Lattice ECP3 devices are suitable for high-volume, high-speed, low-cost applications.
Lattice ProcessorPM™ POWR605 16-Macrocell PLD
The Lattice ProcessorPM™ POWR605 16-Macrocell Progammable Logic Device (PLD) integrates reset generator ICs, voltage supervisor ICs, and watchdog timer ICs on one device. The Lattice ProcessorPM POWR605 features six precision programmable threshold monitors that can be configured to monitor any supply rail from 0.67V to 5.7V and a 16-Macrocell PLD that can be used for generating reset signals and brown-out signals. The Lattice ProcessorPM POWR605 also includes four timers for reset pulse stretching, de-bouncing reset switches, and implementing watchdog timers. This 16-Macrocell PLD can be programmed in-system through JTAG, and the configuration is stored in the on-chip non-volatile E2CMOS® memory. The ispPAC®-POWR607 is an evaluation kit that demonstrates the functions of the POWR605 PLD.
Lattice LatticeXP2 Non-Volatile Field Programmable Gate Arrays
Lattice's LatticeXP2 non-volatile field programmable gate arrays combine a look-up table-based FPGA fabric with Flash non-volatile cells in a flexiFlash™ architecture. The flexiFlash architecture provides instant-on, small footprint, on-chip storage with FlashBAK™ embedded block memories, Serial TAG memory, and design security. The devices include LUT-based logic, distributed and embedded memory, Phase Locked Loops, pre-engineered source synchronous I/O, and enhanced sysDSP blocks. The product is ideal for high-volume, low-cost applications.
Lattice LatticeECP2/M™ FPGAs
Lattice's LatticeECP2™ and LatticeECP2M™ families of field programmable gate arrays (FPGAs) integrate high-performance FPGA features in a low cost device. The ECP2 family features high-performance DSP blocks, up to 70K LUT capacity, support for DDR2 memory interfaces at 533Mbps and up to 840Mbps generic LVDS performance. The ECP2M offers embedded SERDES, 100K LUT, and memory capacity up to 5.3Mbits.