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Home » Applications & Technologies » Low-Power Analog Design
Applications & Technologies

Low-Power Analog Design

By John Donovan, Mouser Electronics

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Once consumers discovered they couldn’t live without battery-powered handheld devices (aka cell phones), low-power design suddenly became the top priority that it remains today. Moore’s Law helped a great deal, but so did a host of other clever innovations including multiple clock and power domains, dynamic voltage and frequency scaling, power gating, and multiple sleep states. All of these techniques are highly effective for digital designs but don’t help at all in the analog domain. Bummer.

Formula 1

The world remains stubbornly analog, as do humans. Devices such as cell phones—which contain a multitude of sensors as well as analog outputs—are challenged to process analog data while retaining signal integrity and low power consumption. Maintaining linearity and low noise in analog circuits generally requires high-gain, power hungry devices. Power is traded off for speed (bandwidth), resolution (linearity), and low noise (SNR). Still, there are numerous design approaches that embedded developers can take that can result in low-power analog devices. There is hope yet for those doing analog and mixed-signal design.

Powering Down

The formula for dynamic power dissipation highlights a few ways to reduce power consumption:

Formula 1

The biggest gain clearly results from lowering the voltage (VDD). Choose an op-amp—all things being equal—with the lowest operating voltage and a rail-to-rail common-mode input range. Then level shift down into the low-voltage core device as early as possible.

Referring again to the formula, you can also reduce the activity (a) of the circuit, usually by clock gating; by reducing the capacitance (C) being toggled; and by reducing the clock frequency (f). Unfortunately these solutions work far better for digital than analog devices, where static power is the primary problem.

Power, speed, and resolution all require tradeoffs. Minimizing power saves energy, simplifies cooling, and contributes to device longevity. High speed can relax resolution and filtering requirements but at the cost of higher power consumption; generally you want just enough speed to accommodate the required signal bandwidth. You need enough resolution to accommodate the system’s dynamic range; higher resolution can relax filtering, but again at the expense of power.

You can’t avoid the tradeoffs but there are ways to minimize their impact. One way is to digitally assist analog circuits, which enables them to achieve high accuracy while remaining low power. For example a digital calibration circuit can analyze the errors in a successive-approximation (SAR) ADC and compensate for them in the background; it could also compensate for the temperature and voltage drifts to which analog circuits are susceptible.

Analog output circuits are subject to offsets due to circuit mismatches. Here a DAC could contribute a small adjustment voltage to correct for the mismatch. Such digital calibration and compensation techniques can result in analog gain stages that don’t require large open-loop gain and thus high current requirements.

Analog Front Ends

In an analog front end (AFE) a single (differential) stage is preferable as long as it meets the system’s gain, bandwidth, and slew rate requirements. Replace Class A op-amps with rail-to-rail common mode Class AB op-amps, which are biased at small currents and thus dissipate less quiescent power. In doing so be careful that you can still provide sufficient gain and output power, maximizing gain while preserving an acceptable bandwidth and slew rate.

If possible, design an op¬-amp circuit using voltage-mode feedback (Figure 1 a) in contrast to current-mode (Figure 1 b). A voltage¬-mode driver typically draws half the power of a current-mode stage; in AC-coupled systems such as PCI Express, SATA, and XAUI that figure drops to 25%.

(a) Voltage-mode feedback op amp and (b) Current-mode feedback op ampFigure 1: (a) Voltage-mode feedback op amp and (b) Current-mode feedback op amp

Digitize the signal as soon as possible. You can often use digital filtering to compensate for a weak analog signal that might otherwise be too close to the noise floor.

Sleep modes are very helpful to reduce energy consumption in digital circuits but must be used cautiously in analog circuits. Because static leakage predominates at smaller line widths, power gating is used to power different voltage islands down or off during sleep modes. This can cause problems with level shifters in mixed-signal designs. To avoid this, a power management IC (PMIC) could preset the control signals to the IDDQ state to eliminate leakage from the analog domain.

Data Conversion

After the AFE amplifies low-level sensor data, it feeds it to an ADC. The choice of an ADC can greatly affect the power profile of an application. It will also dictate the choice of the op-amp that drives it.

High resolution sigma-delta (or delta-sigma) ADCs are common in low-frequency applications. However to conserve power and die size, simpler is better. In a successive-approximation (SAR) ADC, no high-gain, high-power precision amplifier is required; so static power consumption is minimized.

Instead of a fast pipelined ADC, a SAR ADC achieves the same results—albeit more slowly—by relying on only a single-stage comparator instead of multiple gain stages. Figure 2 below shows two Analog Devices, 2-channel ADCs—an AD7911 SAR ADC and an AD9643 pipelined ADC. The pipelined version draws 750 mW at 250 MSPS; the SAR version draws 4 mW at 250 kSPS. If high precision and a high sampling rate aren’t required, then choose a SAR ADC.

On the left, an AD7911 SAR ADC and on the right, an AD9643 pipelined ADC. If high precision and a high sampling rate aren’t required, then choose a SAR ADC.Figure 2: On the left, an AD7911 SAR ADC and on the right, an AD9643 pipelined ADC. If high precision and a high sampling rate aren’t required, then choose a SAR ADC.

Power Supply Considerations

For starters, mixed-signal circuits must have separate analog and digital ground planes to help prevent noise from digital components entering the analog system. For the same reason all digital outputs should be routed away from analog inputs.

A ground plane may seem like a simple concept, but many different currents can typically be flowing in a ground plane. ADCs need an analog ground plane that isn’t shared by any digital circuit, preferably in a separate layer on the PCB; the two ground planes should be tied together only at one point, if possible at the ADC’s digital output driver ground pin. All bypass, reference, and filter capacitors as well as ADC ground connections must be tied to the analog ground plane—and as close together as possible, with the bypass caps next to the supply pin to shunt AC currents to ground as soon as possible.

Even battery-powered devices may incorporate one or more switching regulators. Their output then feeds into a linear regulator, which may or may not be able to filter out all residual ripple and spikes¬—which spells trouble for analog devices, especially those working at low voltages. Judicious layout and extensive use of bypass capacitors and ferrite beads go a long way toward addressing the problem.

Low-Power Analog is Achievable

Low-power analog is not a misnomer; it’s definitely achievable by following some simple design guidelines as well as some not-so-simple digital workarounds. Semiconductor companies like Microchip, Freescale, and Silicon Labs are rising to the challenge by integrating more and more analog components into their MCUs, implementing the digital assists mentioned in this article (so called “smart analog”). With most new devices involving mixed-signal processing, embedded designers will be well rewarded to look further into methods for achieving low-power analog designs.

John Donovan is editor/publisher of www.low-powerdesign.com and ex-Editor-in-Chief of Portable Design, Managing Editor of EDN Asia, and Asian editor of Circuits Assembly and Printed Circuit Fabrication. He has 30 years experience as a technical writer, editor and semiconductor PR flack, having survived earlier careers as a C programmer and microwave technician. John has published two books, dozens of manuals and hundreds of articles. He is a member the Association for Computing Machinery (ACM) and a Senior Member of the IEEE. His favorite pastimes include ham radio, playing with his kids and scouting Texas for the best BBQ joints.

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