Altera Corporation is the pioneer of programmable logic solutions, enabling system and semiconductor companies to rapidly and cost effectively innovate, differentiate, and win in their markets. Altera offers FPGAs, SoC FPGAs, CPLDs, and ASICs in combination with software tools, intellectual property, embedded processors and customer support to provide high-value programmable solutions to customers worldwide.
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Altera's ESW-SOCEDS-DS5-FIX ARM DS-5 SoC Embedded Design Suite is a comprehensive software development tool designed for use with Altera's SoC FPGA's. This suite allows hardware and software teams to work independently and follow their familiar design flows. It takes the Altera Quartus II/Qsys out files and generates handoff files for the software design flow. This removes the debugging barrier between CPUs and the FPGA. The DS-5 Suite is the industry's most advanced debugger for ARM based devices. It has a JTAG based system-level debugging and gdbserver-based application debugging in one package.
Altera® offers a variety of hardware solutions and tools to accelerate the design process. The Stratix® Series FPGA Development Tools offer a wide range of development kits that contain everything an engineer needs to create and implement a design in hours. These development kits deliver a complete system-level design environment that includes both the hardware and software needed to immediately begin developing FPGA designs.
Altera SoC FPGAs integrate an ARM-based hard processor system (HPS) consisting of processor, peripherals, and memory interfaces with the FPGA fabric using a high-bandwidth interconnect backbone. They combine the performance and power savings of hard intellectual property (IP) with the flexibility of programmable logic. These user-customizable ARM-based SoC FPGAs are ideal for reducing system power, cost, and board size by integrating discrete processors and digital signal processing (DSP) functions into a single FPGA. They differentiate the end product with custom hardware and software and add support for virtually any interface standard or protocol in the FPGA. Altera's SoC FPGAs extend product life and revenue through hardware and software updates in the field. They also improve system performance via high-bandwidth interconnect between the processor and the FPGA. These devices join the diverse family of Cyclone® V and Arria® V FPGAs with dozens of devices and variations and include additional hard logic such as PCI Express® Gen2, multiport memory controllers, and high-speed serial transceivers. Built on TSMC's 28nm Low-Power (28LP) process, the SoC FPGAs drive down power and cost while enabling performance levels required by cost-sensitive applications.
Altera® offers a variety of hardware solutions and tools to accelerate the design process. The Arria® Series FPGA Development Tools offer a wide range of development kits that contain everything an engineer needs to create and implement a design in hours. These development kits deliver a complete system-level design environment that includes both the hardware and software needed to immediately begin developing FPGA designs.
Altera's Stratix® II & GX High Performance FPGAs allows designers to implement your high-density logic design and get high performance and great signal integrity in the most efficient device possible. Whether your design is for a single device to prototype an ASIC, or is destined for volume production, you'll benefit from knowing you can move from your Stratix II FPGA to a HardCopy® II ASIC whenever business conditions require it. Other key Stratix® II FPGA features include an innovative logic structure, a rich feature set including high-performance DSP blocks and on-chip memories, high-speed I/O pins and external memory interfaces, a design security feature to protect your intellectual property (IP), a path to low-cost, high-density logic with a HardCopy® II ASIC.
Altera's Stratix® IV High Density High Performance FPGAs deliver a breakthrough level of system bandwidth and power efficiency for high-end applications, allowing you to innovate without compromise. The Stratix IV device family contains three optimized variants to meet different application requirements. The Stratix IV E (Enhanced) FPGAs—up to 813,050 logic elements (LEs), 33,294 kilobits (Kb) RAM, and 1,288 18 x 18 bit multipliers. The Stratix IV GX transceiver FPGAs—up to 531,200 LEs, 27,376 Kb RAM, 1,288 18 x 18-bit multipliers, and 48 full-duplex clock data recovery (CDR)-based transceivers at up to 8.5 Gbps. The Stratix IV GT—up to 531,200 LEs, 27,376 Kb RAM, 1,288 18 x 18-bit multipliers, and 48 full-duplex CDR-based transceivers at up to 11.3 Gbps.
Altera's Stratix® V High Bandwidth FPGAs deliver the industry's highest
bandwidth, highest level of system integration, and ultimate flexibility
with reduced cost and the lowest total power for high-end applications.
Advantages of the Stratix® V include the ability to attain breakthrough
bandwidth with power-efficient transceivers, achieve higher integration
on a single chip and reduce costs, get ultimate flexibility in your
designs and lower your system power. The Stratix® V is offered in four
Altera Cyclone® IV FPGAs extend the Cyclone FPGA series leadership in
providing the market's lowest-cost, lowest-power FPGAs, now with a
transceiver variant. Cyclone IV devices are targeted to high-volume,
cost-sensitive applications, enabling system designers to meet
increasing bandwidth requirements while lowering costs. Providing power
and cost savings without sacrificing performance, along with a low-cost
integrated transceiver option, Cyclone IV devices are ideal for
low-cost, small-form-factor applications in the wireless, wireline,
broadcast, industrial, consumer, and communications industries. Built on an optimized low-power process, the Altera Cyclone IV device
family offers two variants. Cyclone IV E offers the lowest power and
high functionality with the lowest cost. Cyclone IV GX offers the lowest
power and lowest cost FPGAs with 3.125Gbps transceivers.
Altera Cyclone® III FPGAs offer an unprecedented combination of low power, high functionality, and low cost to maximize your competitive edge. The features and architecture of the Altera Cyclone III FPGA family provides the ideal solution for your high-volume, low-power, cost-sensitive applications. With densities ranging from about 5,000 to 200,000 logic elements (LEs) and 0.5 Megabits (Mb) to 8 Mb of memory for less than ¼ watt of static power consumption, Cyclone III device family makes it easier for you to meet your power budget. To address your unique design needs, this FPGA family offers two variants: Cyclone III provides the lowest power and high functionality with the lowest cost. Cyclone III LS provides the lowest power FPGAs with security.
Altera Cyclone® II 90 nm FPGAs are built from the ground up for low cost and to provide a customer-defined feature set for high-volume, cost-sensitive applications. Cyclone II FPGAs deliver high performance and low power consumption at a cost that rivals that of ASICs. Cyclone II FPGAs extend the low-cost FPGA density range to 68,416 logic elements (LEs) and provide up to 622 usable I/O pins and up to 1.1 Mbits of embedded memory. Cyclone II FPGAs are manufactured on 300-mm wafers using TSMC's 90-nm low-k dielectric process to ensure rapid availability and low cost. By minimizing silicon area, Cyclone II devices can support complex digital systems on a single chip at a cost that rivals that of ASICs. Altera Cyclone II FPGAs offer 60% higher performance and half the power consumption of competing 90-nm FPGAs. The low cost and optimized feature set of Cyclone II FPGAs make them ideal solutions for a wide array of automotive, consumer, communications, video processing, test and measurement, and other end-market solutions.
Altera Cyclone® V 28 nm FPGAs provide the industry's lowest system cost and power, along with performance levels that make the device family ideal for differentiating your high-volume applications. You'll get up to 40 percent lower total power compared with the previous generation, efficient logic integration capabilities, integrated transceiver variants, and SoC FPGA variants with an ARM-based hard processor system (HPS). The family comes in six targeted variants:
Altera Cyclone® Family FPGAs are built to meet your low-power, cost-sensitive design needs, enabling you to get to market faster. Each generation of Cyclone FPGAs solves the technical challenges of increased integration, increased performance, lower power, and faster time to market while meeting cost-sensitive requirements.
Altera Cyclone V FPGAs provide the market's lowest system cost and lowest power FPGA solution for applications in the industrial, wireless, wireline, broadcast, and consumer markets. The family integrates an abundance of hard intellectual property (IP) blocks to enable you to do more with less overall system cost and design time. The SoC FPGAs in the Cyclone V family offer unique innovations such as a hard processor system (HPS) centered around the dual-core ARM® Cortex™-A9 MPCore™ processor with a rich set of hard peripherals to reduce system power, system cost, and board size.
Altera Cyclone IV FPGAs are the lowest cost, lowest power FPGAs, now with a transceiver variant. The Cyclone IV FPGA family targets high-volume, cost-sensitive applications, enabling you to meet increasing bandwidth requirements while lowering costs.
Altera Cyclone III FPGAs offer an unprecedented combination of low cost, high functionality, and power optimization to maximize your competitive edge. The Cyclone III FPGA family is manufactured using Taiwan Semiconductor Manufacturing Company's low-power process technology to deliver low power consumption at a price that rivals that of ASICs. Altera Cyclone II FPGAs are built from the ground up for low cost and to provide a customer-defined feature set for high-volume, cost-sensitive applications.
Altera Cyclone II FPGAs deliver high performance and low power consumption at a cost that rivals that of ASICs.
Altera® Quartus® II design software is a multi-platform design
environment that easily adapts to your specific needs in all phases of
FPGA and CPLD design. Quartus II software delivers the highest
productivity and performance for Altera FPGAs, CPLDs, and HardCopy®
ASICs. This software is available in a free Web Edition or an annual Subscription Edition. This version supports Microsoft Windows XP, Windows 7 (32 and 64 bit), Red Hat Enterprise Linux 6.0 (64 bit), Red Hat Enterprise Linux 5.0 (32 and 64 bit) and SUSE Linux Enterprise 11 SP1 (32 and 64 bit) operating systems.
Altera Arria® V Midrange FPGAs consists of the most comprehensive offerings of
mid-range FPGAs ranging from the lowest power for 6-gigabits per second
(Gbps) and 10-Gbps applications, to the highest mid-range FPGA bandwidth
12.5 Gbps transceivers. The Arria® V devices are ideal for
power-sensitive wireless infrastructure equipment, 20G/40G bridging,
switching, and packet processing applications, high-definition video
processing and image manipulation, and intensive digital signal
processing (DSP) applications.
Altera MAX 3000A 3.3-V CPLDs are cost-optimized, EEPROM-based family that provides instant-on capability and offers densities from 32 to 512 macrocells. MAX 3000A CPLDs support in-system programmability (ISP) and can be easily reconfigured in the field. Each MAX 3000A macrocell is individually configurable for either sequential or combinatorial logic operation. Altera's MAX 3000A programmable logic devices are the ideal non-volatile, instant-on CPLDs for high-volume, cost-sensitive applications.
Altera Arria® II GX and GZ Low Power 6G Transceiver FPGAs deliver
substantial cost and power savings over competing devices, while
providing high functionality for 6G transceiver-based applications. The
40-nm Arria II family includes the lowest cost FPGA with 6.375-Gbps
transceivers and devices with up to 50 percent lower static power vs.
the competition. The Arria II GX FPGAs have up to 16 6.375-Gbps
transceivers, LVDS at 1.25 Gbps, and support for 400 MHz DD3. The Arria
II GZ FPGA offers up to 24 6.375-Gbps transceivers, more density and
memory, and higher digital signal processing (DSP) capabilities than
Arria II GX FPGAs.
Altera's Arria® FPGA series is designed for cost- and power-sensitive transceiver-based and embedded applications. The Arria FPGA series has a rich feature set of memory, logic, and digital signal processing (DSP) blocks combined with the superior signal integrity of up to 12.5 Gbps transceivers to allow you to integrate more functions and maximize system bandwidth. Furthermore, the SoC FPGAs in the Arria V device family offer an ARM-based hard processor system (HPS) for even higher integration and power savings. The Arria series includes Arria GX, Arria II, and Arria V devices which have always had on-chip transceivers that allow the transfer of serial data in and out of the FPGA at high frequencies. The newest member to the Arria series is the Arria V GZ FPGA offering the highest bandwidth of any mid-range FPGA with its integrated 12.5 Gbps backplane-capable transceivers.
Altera MAX® II CPLD family devices are the lowest power, lowest cost CPLDs ever. Altera MAX II CPLD family is based on a groundbreaking architecture that delivers the lowest power and the lowest cost per I/O pin of any CPLD family. With the introduction of the MAX IIZ CPLD, there are now three variants that all use the same innovative CPLD architecture: MAX II, MAX IIG, and MAX IIZ. Zero-power MAX IIZ CPLDs offer the same non-volatile, instant-on advantages found in the low-cost MAX II CPLD family and are applicable to a wide range of functions and applications. MAXII is an instant-on, non-volatile CPLD family that targets general-purpose, low-density logic and portable applications, such as cellular handset design.
Altera's Stratix® III High Performance FPGAs provide the world's highest performance and highest density 65-nm FPGA combined with the lowest possible power consumption. A Stratix® III FPGA will provide the high-performance and high-integration capabilities needed for next-generation basestations, network infrastructure, and advanced imaging equipment. Specifically designed for ease of use and rapid system integration, the Stratix® III FPGA family offers two variants optimized to meet different application needs. The Stratix® III L family provides balanced logic, memory, and multiplier ratios for mainstream applications. The Stratix® III E family is memory- and multiplier-rich for data-centric applications.
Altera MAX® V CPLDs deliver the industry's best value in low cost, low power CPLDs, offering robust new features at up to 50% lower total power when compared to competitive CPLDs. Altera MAX V also features a unique, non-volatile architecture and one of the industry's largest density CPLDs. In addition, the MAX V integrates many functions that were previously external, such as flash, RAM, oscillators, and phase-locked loops, and in many cases, it delivers more I/Os and logic per footprint at the same price as competitive CPLDs. The MAX V utilizes green packaging technology, with packages as small as 20 mm2. MAX V CPLDs are supported by Quartus II® Software v.10.1, which allows productivity enhancements resulting in faster simulation, faster board bring-up, and faster timing closure.
Altera MAX™ complex programmable logic device (CPLD) Series provides you with the lowest power, lowest cost CPLDs. MAX V CPLD family, the newest family in the CPLD series, delivers the market's best value. Featuring a unique, non-volatile architecture and one of the industry's largest density CPLDs, MAX V devices provide robust new features at lower total power compared to competitive CPLDs. MAX II CPLD family, based on the same groundbreaking architecture, delivers low power and low cost per I/O pin. MAX II CPLDs are instant-on, non-volatile devices that target general-purpose, low-density logic and portable applications, such as cellular handset design. Zero power MAX IIZ CPLDs offer the same non-volatile, instant-on advantages found in the MAX II CPLD family and are applicable to a wide range of functions. Manufactured on an advanced 0.30-µm CMOS process, the EEPROM-based MAX 3000A CPLD family provides instant-on capability and offers densities from 32 to 512 macrocells.
The Stratix® FPGA family, Altera's first generation of high-end FPGA families, combined an architecture tuned for high performance with the highest level of integration available on an FPGA from any vendor. A Stratix® FPGA can provide up to 80K logic elements (LEs) and 7.3 Mbits of on-chip RAM arranged in TriMatrix™ memory blocks, operating at up to 350 MHz. The Stratix® FPGA supports external memory interfaces such as DDR SDRAM at 400 Mbps and QDRII SRAM at 800 Mbps. The Stratix® FPGA also introduced the world's first digital signal processing (DSP) block, containing four 18 x 18 multipliers, accumulators, and a summation unit. Building on the Stratix® FPGA high-performance architectural features, the Stratix® GX FPGA is the first programmable logic device to incorporate high-speed serial transceivers operating at multi-gigabit speeds. Using a transceiver block supporting four full-duplex channels and clock data recovery (CDR) technology allows transmission of data in excess of 3.1875-Gbps per channel.
Altera's Stratix® FPGA Family enables you to deliver high-performance, state-of-the-art products to market faster with lower risk and higher productivity. By combining high density, high performance, and a rich feature set, Stratix series FPGAs allow you to integrate more functions and maximize system bandwidth. Both evolutionary and revolutionary features have been incorporated over the generations of Stratix FPGA families. Stratix FPGAs have HardCopy® ASIC equivalent devices. HardCopy ASICs provide a path to low-cost volume production with low risk through FPGA prototyping of your design. Stratix series FPGAs are also ideal for the prototyping and verification of standard-cell ASICs.
Quartus II FPGA design software offers a complete software design solution for all Altera devices, including the following features:
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Designers need access to a wide variety of IP blocks of differing size and complexity, from the basic arithmetic blocks to transceivers, memory controllers, microprocessors, signal processing, and protocol interfaces. Altera and its third-party IP partners offer a broad portfolio of off-the-shelf, configurable IP cores optimized for Altera® devices. Licensed and unlicensed IP is delivered and installed with Altera's Quartus® II design software. Partner IP can be requested directly from this website. Use the technology links in the left-hand navigation or the search box below to find available Altera and Partner IP for your next design.
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Reference designs enable true design reuse and fast time to market by serving as technical sub-system or system blueprints, often for targeted applications. Altera and its partners develop and deliver reference designs that show efficient solutions for common system design problems. These reference designs are downloadable directly from this website or can be requested using the automated request form.
Altera's broad product portfolio supports a wide range of markets.
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