High speed, low power analog-to-digital converters (ADCs) which includes JESD204B interface.
Low-noise, low-drift, ΔΣ ADCs with
an integrated PGA, reference, and internal fault monitors.
High-linearity, ultra-low power, dual-channel, 12-bit, 50MSPS to 160MSPS, ADCs.
A 16-bit 250kSPS ADC optimized for low-power operation and power consumption scales directly with speed.
Ultra-low power ultra-small analog-to-digital converters that includes a capacitor-based SAR ADC.