Low skew, high-speed 1 input to 4 output clock buffers with sub 50fsec Additive Phase Jitter.
Best-in-class sub-50 fsec RMS additive phase jitter (12KHz to 20MHz), with Output Enable function.
SoC, PCIe Gen1-2-3; up to a 90% reduction in power consumption & board space vs. standard 3.3V
Low-cost five output 3.3V clock buffer designed for low power consumption; less than 32mA at 66.6MHz with unloaded outputs.
High performance 2:1 multiplexer features differential inputs that accept LVPECL & LVDS levels.