V1 ColdFire® Core Brings 8-bit Ease of Use to 32-bit Performance

Designed for entry-level 32-bit applications, the V1 ColdFire core is a simplified version of the V2 ColdFire core, featuring the same address modes and instruction definitions. It is a memory-configurable hierarchical architecture that is 100-percent synthesizable, specifically designed for reuse and ease of integration into custom designs.

The 32-bit core supports up to 150MHz of performance using a standard cell-based design methodology in a generic 130-nm process technology and interfaces to the System-on-Chip (SoC) using the standard AMBA-AHBbus. The core supports a variable-length RISC architecture that allows instructions to be 16, 32 or 48 bits in length. The result is more efficiently packed code in memory, reducing memory requirements and lowering overall system cost.

The V1 core is an ideal entry point to 32-bit performance. All ColdFire cores (V1, V2, V3 and V4) share the same architecture and instruction set, making upward compatibility to other ColdFire cores a smooth roadmap to higher performance designs.

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V1 Coldfire Fact Sheet

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Target Applications

• Consumer electronics
• Handheld and remote terminals
• Healthcare instruments and monitoring equipment
• Factory automation systems
• Building monitor and control systems
• Security/access systems
• Office/home automation

• L32-bit core with 32-bit address bus for improved access performance to local flash and RAM
• Single-wire background debug module (BDM) interface with on-chip-in-circuit emulator (ICE) debug module
• Increased operand handling for 8- and 16-bit
• Optional multiply-accumulate (MAC) and enhanced MAC (eMAC)
• Enhanced general purpose input/output (GPIO) capabilities

V2 ColdFire® Core - opening the door to 32-bit control

The ColdFire® V2 core is based on a memory-configurable hierarchical architecture that is 100 percent synthesizable and specifically designed for reuse and ease of integration into custom designs. The core supports up to 166 MHz of performance on a 0.13 µm process using a single-issue, standard cell-based design with 32-bit address and data buses and an integrated debug module. The core uses a variable length RISC architecture that allows instructions to be 16, 32, or 48 bits in length. The result is more efficiently packed code in memory, reducing memory requirements and lowering overall system costs.

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V3 ColdFire® Core - Single-Issue + Pipelined Local Bus

The ColdFire 3 core delivers enhancements including a refined instruction prefetch pipeline, branch prediction capabilities, and higher frequencies of operation. These improvements allow the core to provide up to 300% more performance than the ColdFire 2/2M core, while increasing the operating system frequency by less than 50%, making it an attractive solution for new designs or upgrades to existing systems. In addition, it includes a high-speed multiply-accumulate unit, dedicated hardware divide, and enhanced debugging capabilities.

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V4 ColdFire® Core - Limited Superscalar

The next-generation ColdFire® micro-architecture provides a 2.8x performance improvement when compared with the ColdFire 3 core over a broad range of applications.

• Improved microarchitecture for higher performance:
  
• greater than 200 Dhrystone 2.1 MIPS @ 150 MHz
• Small set of new instructions for better code density and performance
• Enhanced MAC and debug functionality
• Core size = 4.5 mm2 in 0.25 micron drawn process
• Independent, decoupled pipelines
• 4-stage Instruction Fetch Pipeline (IFP)
• 5-stage Operand Execution Pipeline
• FIFO I-Buffer is the decoupling mechanism
• Limited superscalar execution through use of instruction folding
• Approaches dual-issue performance but at a much lower silicon cost
• Harvard memory architecture
• Most instructions execute in 1 cycle
• Sophisticated 2-level branch acceleration mechanisms in the IFP minimize execution time of change

V4e ColdFire® Core

The V4e is designed to provide hardware support for on-chip multiprocessing for systems requiring intensive numeric processing capabilities beyond that provided by a single processor. Designs implemented in 0.18 micron technology are expected to provide 350 Dhrystone 2.1 MIPS of processing power per core when operating at 225 MHz, while migrating to 0.13 micron technology boosts the performance level to 333 MHz and up to 510 Dhrystone 2.1 MIPS per core.

The V4e is an IP Core which will be integrated into a variety of custom and standard products from Freescale. There currently are no plans for a standalone CPU version.

• High performance IP Core for the 68K/ColdFire family
• Partial superscalar execution
• Harvard memory architecture resulting in enhanced bandwidth
• Support for variable sized instruction caches and data caches
• Minimal change-of-flow program execution time via sophisticated 2 level branch acceleration
• Virtual memory management unit (MMU)
• Address translation inside the core complex
• Process partitioning
• Expanded debug capabilities
• Harvard, dual 32-entry, fully-associative TLBs
• Floating point unit (FPU)
• Double-precision implementation of the MC68060 FP ISA
• Concurrent execution between Operand Execution Pipeline & FPU
• IEEE-754 compliant
• Enhanced multiply accumulate unit (MAC)
• Single-cycle issue, optimized for 32x32 MACs
• Four 48-bit accumulators
• Expanded programming model
• Dual-port RAM with user-defined address permutation
• Hardware support for on-chip multiprocessing

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