The AT32UC3A0512 and AT32UC3A1512, the first devices available, deliver 80 Dhrystone MIPS (DMIPS) at 66 MHz and consume only 40 mA at 3.3V. The power consumption, as low as 1.65 mW/DMIPS, outperforms by a ratio of 1.7 to 4.3 other available architectures offering similar feature sets and lower processing performances. The standby power consumption of UC3A Series is just 40 micro-Amps.

The AVR32 UC core is the second core to be based on the Atmel AVR32 architecture, launched in 2006. It has single cycle DSP instructions that include multipliers and multiply-and-accumulate, and executes 1.3 DMIPS/MHz.

BUS ARCHITECTURE - Six Layer Bus Architecture with Dynamic Frequency Scaling – UC3A Series MCUs have a six-layer high speed bus matrix with point-to-point connections from all masters to all slaves, enabling masters to concurrently access any slave at a maximum speed of 264M bytes per second at 66 MHz. If multiple masters wish to access the same slave, arbitration is automatically performed. The bus masters in UC3A Series devices are the AVR32 UC core data and instruction interfaces, peripheral DMA controller, and several high speed peripherals such as the Ethernet MAC and USB. The bus slaves are the on-chip SRAM and Flash memories, USB, the two peripheral bus bridges, and the external bus interface (EBI).

PERIPHERAL SET Matches that of Atmel's ARM-based Controllers – The UC3A Series MCU family utilizes many of the same features Atmel developed for its SAM7 and SAM9 families of ARM-based MCUs including the peripheral DMA controller, multi-layer high speed bus architecture, Ethernet MAC, analog to digital converter and serial communication peripherals.

USB OTG – A full speed (12 Mbps) USB 2.0 device with On-The-Go (OTG) capability has dedicated DMA, can interface to a personal computer as a device, and can behave as a USB host to support small USB devices such as USB Flash keys, printers, keyboards or mice. The USB device has a dedicated memory that supports seven software configurable end-points so several USB classes can run simultaneously.

Communications interfaces include two master/slave serial parallel interfaces (SPIs), one synchronous serial controller (SSC), one master/slave two-wire interface (I2C compatible) and four USARTs with hardware flow-control. One USART has special extensions to support modem, IrDA and smart-card ISO7816 serial protocols.

UC3A Series microcontrollers are available with an external bus interface (EBI) that extends the addressable physical memory to 16M bytes. Its non-multiplexed 16-bit data bus can interface to high density external SRAM, SDRAM, ROM, Flash devices and memory-mapped devices such as LCDs or FPGAs.

Devices have three 16-bit timers and seven pulse width modulators (PWM) that can trigger the 10-bit 8-channel ADC to ease electrical motor control design.

ON-CHIP SYSTEM MANAGER – The on-chip system manager includes an internal voltage regulator for 3.3V single power supply operation, power-on reset, brown-out detector, hardware watchdog timer and a real-time timer. The clock system provides an on-chip RC oscillator, 2 high frequency external oscillators, one 32 kHz oscillator and two independent on-chip PLLs. Special security options are available to protect Flash content from being corrupted by the application itself or from being read from external unauthorized access.