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Alliance Memory
   
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Alliance Memory, Inc. is a fabless semiconductor company specializing in Fast Asynchronous products, including low power SRAM and SDRAM. Alliance Memory features a Fast SRAM line-up that includes densities ranging from 64k to 4M Fast SRAM in both the x8 and x16 configuration. Alliance Memory's product line of legacy memories supports the industrial and communications markets.

 
Alliance Memory Newest Products

Alliance Memory Product Line

Alliance Memory New Products

Added 04/2014 Alliance Memory Mobile DDR Learn More
Added 03/2014 Alliance Memory DDR3 Synchronous DRAM Learn More
Added 01/2014 Alliance Memory Synchronous DRAM Learn More
Added 01/2014 Alliance Memory DDR1 Synchronous DRAM Learn More
Added 12/2012 Alliance Memory Low Power CMOS SRAM Learn More
Added 07/2012 Alliance Memory AS7C256A SRAM Learn More
Added 03/2012 Alliance Memory AS4C Series SDRAM Learn More
Added 04/2011 Alliance Memory Low Power SRAM - New At Mouser Learn More
Added 04/2011 Alliance Memory Fast Asynchronous SRAM - New At Mouser Learn More

Alliance Memory Featured Products

Alliance Memory DDR2 Synchronous DRAM

Alliance Memory DDR2 Synchronous DRAM is designed to comply with DDR2 DRAM key features such as posted CAS# with additive latency, Write latency = Read latency -1 and On Die Termination(ODT). All of the control and address inputs are synchronized with a pair of externally supplied differential clocks. Inputs are latched at the cross point of differential clocks (CK rising and CK# falling). All I/Os are synchronized with a pair of bidirectional strobes (DQS and DQS#) in a source synchronous fashion. The address bus is used to convey row, column, and bank address information in RAS #, CAS# multiplexing style. Accesses begin with the registration of a Bank Activate command, and then it is followed by a Read or Write command. Read and write accesses to the DDR2 SDRAM are 4 or 8-bit burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Operating the eight memory banks in an interleaved fashion allows random access operation to occur at a higher rate than is possible with standard DRAMs. An auto precharge function may be enabled to provide a self-timed row precharge that is initiated at the end of the burst sequence. A sequential and gapless data rate is possible depending on burst length, CAS latency, and speed grade of the device.

Alliance Memory DDR1 Synchronous DRAM

Alliance Memory DDR1 Synchronous DRAM is a high-speed CMOS double data rate synchronous DRAM. It is internally configured with a synchronous interface (all signals are registered on the positive edge of the clock signal, CK). Data outputs occur at both rising edges of CK and CK . Read and write accesses to the SDRAM are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of a BankActivate command which is then followed by a Read or Write command. Accesses begin with the registration of a BankActivate command which is then followed by a Read or Write command. The DDR SDRAM provides programmable Read or Write burst lengths of 2, 4, or 8. An auto precharge function may be enabled to provide a self-timed row precharge that is initiated at the end of the burst sequence. The refresh functions, either Auto or Self Refresh are easy to use. In addition, The DDR SDRAM features programmable DLL option. By having a programmable mode register and extended mode register, the system can choose the most suitable modes to maximize its performance. These devices are well suited for applications requiring high memory bandwidth and high performance.

Alliance Memory DDR3 Synchronous DRAM

Alliance Memory DDR3 Synchronous DRAM (SDRAM) achieve high speed double-data-rate transfer rates of up to 1600 Mb/sec/pin for general applications. The chip is designed to comply with all key DDR3 DRAM key features and all of the control and address inputs are synchronized with a pair of externally supplied differential clocks. Inputs are latched at the cross point of differential clocks (CK rising and CK# falling). All I/Os are synchronized with differential DQS pair in a source synchronous fashion. These devices operate with a single 1.5V ± 0.075V power supply and are available in BGA packages.

Alliance Memory Mobile DDR

Alliance Memory Mobile DDR is fabricated with high performance CMOS technology. Mobile DDR uses a double data rate architecture to achieve high-speed operation. The double data rate architecture is essentially a 2n-prefetch architecture with an interface designed to transfer two data words per clock cycle at the I/O balls. Range of operating frequencies, programmable burst lengths and programmable latencies allow the same device to be useful for a variety of high bandwidth and high performance memory system applications.

Alliance Memory Low Power CMOS SRAM

Alliance Memory Low Power Static Random Access Memory (SRAM) devices are fabricated using high performance, high reliability CMOS technology. Alliance Memory CMOS SRAM devices are designed for low-power applications and are particularly well-suited for battery back-up nonvolatile memory applications. AS6C8008 is a 8,388,608-bit device organized as 1,048,576 words by 8 bits. AS6C1616 is a 16,777,216-bit device organized as 1,048,576 words by 16 bits. AS6C6264A is a 65,536-bit device organized as 8,192 words by 8 bits. AS6C62256 is a 262,144-bit device organized as 32,768 words by 8 bits.

Alliance Memory AS4C Series SDRAM

Alliance Memory AS4C Series SDRAM are high-speed CMOS synchronous DRAM containing 64, 128, or 256 Mbits. They are internally configured as 4 Banks of 1M, 2M, or 4M word x 16 DRAM with a synchronous interface (all signals are registered on the positive edge of the clock signal, CLK). Read and write accesses to the SDRAM are burst oriented; accesses start at selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of a BankActivate command which is then followed by a Read or Write command.

Alliance Memory AS4C Series SDRAM provides for programmable Read or Write burst length of 1, 2, 4, 8, or full page, with a burst termination option. An auto precharge function may be enabled to provide a self-timed row precharge that is initiated at the end of the burst sequence. The refresh functions, either Auto or Self Refresh are easy to use. By having a programmable mode register, the system can choose the most suitable modes to maximize its performance. These devices are well suited for applications requiring high memory bandwidth and particularly well suited to high performance PC applications.

Alliance Memory Low Power SRAM

Alliance Memory Low Power SRAM devices feature a fast access time of 70 ns and low power consumption. The Alliance Memory AS6C1616 is a 16,777,216-bit low power CMOS SRAM organized as 1,048,576 words by 16 bits. The AS6C1616 features a 30mA typical operating current and operates for a single power supply of 2.7V to 3.6V. The Alliance Memory AS6C62256A is a 32,768x8 bit static CMOS SRAM device with read, write, standby, and data retention operating modes. It features a typical operating supply current of 50mA. These SRAM devices are ideally suited for low power applications, including battery back-up nonvolatile memory applications.

Alliance Memory Fast Asynchronous SRAM

Alliance Memory AS7C256A and AS7C4096A are high-performance CMOS Fast Asynchronous SRAM devices designed for memory applications in which fast data access and low power are desired. The Alliance Memory AS7C256A is a 5.0V 262,144-bit device organized as 32,768 words x 8 bits. This fast asynchronous SRAM device is ideal for Pentium™, PowerPC™, and portable computing applications. It provides 5.0V operation without sacrificing performance or operating margins. The Alliance Memory AS7C4096A is a 4,194,304-bit device organized as 524,288 words x 8 bits. This fast asynchronous SRAM device features equal address access and cycle times of 10/12/15/20 ns with output enable access times of 5/6 ns, making it ideal for high-performance applications. These Alliance Memory devices feature chip enable input that permits easy memory expansion with multiple-bank memory systems.

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